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duram.v
module duram(
data_a,
data_b,
wren_a,
wren_b,
address_a,
address_b,
clock_a,
clock_b,
q_a,
q_b);
parameter DATA_WIDTH = 36;
parameter ADDR_WIDTH = 9;
parameter BLK_RAM_TYPE = "AUTO";
parame
duram.v
module duram(
data_a,
data_b,
wren_a,
wren_b,
address_a,
address_b,
clock_a,
clock_b,
q_a,
q_b); //synthesis syn_black_box
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 5;
parameter BL
timescale.v
//////////////////////////////////////////////////////////////////////
//// ////
//// timescale.v
glbl.v
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
wire GSR;
wire GTS;
wire PRLD;
reg GSR_int;
reg GTS_int;
ddr_in.v
/*-----------------------------------------------------------------------------
-- Double Data Rate (DDR) --
-- Input DDR inferen
mult_and.v
/*-----------------------------------------------------------------------------
-- Virtex-II MULT_AND cell inference using Synplify --
--------------------------------------
dcm.v
/*-----------------------------------------------------------------------------
-- Digital Clock Manager (DCM) --
-- DCM in de-skew mode
alu.v
module alu(clk, a, b, opcode, outp);
input clk;
input [7:0] a, b;
input [2:0] opcode;
output [7:0] outp;
reg [7:0] outp;
always @(posedge clk)
begin
case (opcode) /* synthesis full_c
define.v
/******************************************************************************
*
* File Name: define.v
* Version: 1.14
* Date: Sept 9, 1999
* Description: define global parameter
unisim.v
module BSCAN_VIRTEX(DRCK1, DRCK2, RESET, SEL1, SEL2, SHIFT, TDI, UPDATE, TDO1, TDO2); // synthesis syn_black_box
input TDO1;
input TDO2;
output TDI;
output RESET;
output SHIFT;
output UPDATE;
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