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V 的代码
datactl.v
//?????
//--------------------------------------------------------------------
module datactl (data,in,data_ena);
output [7:0]data;
input [7:0]in;
input data_ena;
assign data = (data_ena)? in
counter.v
//?????
//------------------------------------------------------------------------------
module counter ( pc_addr, ir_addr, load, clock, rst);
output [12:0] pc_addr;
input [12:0] ir_addr;
input l
machinectl.v
//?????
//------------------------------------------------------------------------------
module machinectl( ena, fetch, rst);
output ena;
input fetch, rst;
reg ena;
always @(posedge fetch or
adr.v
//?????
//------------------------------------------------------------------------------
module adr(addr,fetch,ir_addr,pc_addr);
output [12:0] addr;
input [12:0] ir_addr, pc_addr;
input fetch;
machine.v
//----------------------------------------------------------------------------
module machine( inc_pc, load_acc, load_pc, rd,wr, load_ir,
datactl_ena, halt, clk1, zero, ena, opcode );
output inc
rom.v
module rom( data, addr, read, ena );
output [7:0] data;
input [12:0] addr;
input read, ena;
reg [7:0] memory [13'h1fff:0];
wire [7:0] data;
assign data= ( read && ena )? memory[addr] : 8'bzzzz
cpu.v
//------------------------------------------- cpu.v ????? -------------------------------------------
/******************************************************************************
*** ?????CP
accum.v
//???
//--------------------------------------------------------------
module accum( accum, data, ena, clk1, rst);
output[7:0]accum;
input[7:0]data;
input ena,clk1,rst;
reg[7:0]accum;
always@
alu.v
//?????
//------------------------------------------------------------------------------
module alu (alu_out, zero, data, accum, alu_clk, opcode);
output [7:0]alu_out;
output zero;
input [7:0] da
ram.v
// --------------- RAM?ROM ----------------------------------------
module ram( data, addr, ena, read, write );
inout [7:0] data;
input [9:0] addr;
input ena;
input read, write;
reg [7:0] ram [1