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V 的代码
register.v
//?????
//---------------------------------------------------------------
module register(opc_iraddr,data,ena,clk1,rst);
output [15:0] opc_iraddr;
input [7:0] data;
input ena, clk1, rst;
reg [15
cputop.v
//------------------------------------------- cputop.v ????? -----------------------------------------------------
/***********************************************************************
*** ?????
tests.v
/////////////////////////////////////////////////////////////////////
//// ////
//// Test Case Collection
excalibur.v
// megafunction wizard: %ARM-Based Excalibur%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ARM-Based Excalibur
// PROJECT: excalibur
// ========================================================
v.c
main (int *p)
{
int a;
a = 0;
p[1] = a;
a = 0;
p[2] = a;
a = 123456;
p[3] = a;
}
asmi.v
//Legal Notice: (C)2005 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic function
sysid.v
//Legal Notice: (C)2005 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic function
asmi.v
//Legal Notice: (C)2005 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic function
sysid.v
//Legal Notice: (C)2005 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic function
duram.v
module duram(
data_a,
data_b,
wren_a,
wren_b,
address_a,
address_b,
clock_a,
clock_b,
q_a,
q_b); //synthesis syn_black_box
parameter DATA_WIDTH = 32;
parameter ADDR_WIDTH = 5;
parameter BL