verilog2.v

来自「基于FPGA火车状态机的实现方法」· Verilog 代码 · 共 62 行

module tb_train();

reg sensor1;
reg sensor2;
reg sensor3;
reg sensor4;
reg sensor5;
reg reset;
reg clock;
wire switch1;
wire switch2;
wire switch3;
reg sensor13;
reg sensor24;
reg sensor12;
wire CLOCK_50;
reg dirB;
reg dirA;

initial begin
  clock=0;
  forever #5 clock=~clock;
  end
  
initial begin
#10 reset=0;
#10 sensor12=00;
#10 sensor12=01;
#10 sensor12=10;
#10 sensor12=11;
#10 sensor13=00;
#10 sensor13=01;
#10 sensor13=10;
#10 sensor13=11;
#10 sensor24=00;
#10 sensor13=01;
#10 sensor13=10;
#10 sensor13=11;
#100 $finish;
end

train train(
           .sensor1(sensor1),
           .sensor2(sensor2),
           .sensor3(sensor3),
           .sensor4(sensor4),
           .sensor5(sensor5),
           .reset(reset),
           .clock(clock),
           .switch1(switch1),
           .switch2(switch2),
           .switch3(switch3)
           );
           
  initial begin
    $fsdbDumpfile ("tb_train.fsdb");
    $fsdbDumpvars ();
  end
  endmodule