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verilog.v
// generated by newgenasym Thu May 10 13:22:43 2001
module high_speed_ram (ra, rcs0, rcs1, rcs2, rcs3, rd, rwe);
input [15:0] ra;
input rcs0;
input rcs1;
input rcs2;
input rcs3;
verilog.v
`timescale 1ns/1ns
module high_speed_ram (rd, ra, rcs0, rcs1, rcs2, rcs3, rwe );
// generated by HDL Direct 14.20-p006 14-Mar-2002
// on Wed May 01 09:04:33 2002
// from project1_lib/HIGH_SPEED_RAM/
vga.v
/* vga.v -- XSOC bilevel VGA controller synthesizable Verilog model
*
* Copyright (C) 1999, 2000, Gray Research LLC. All rights reserved.
* The contents of this file are subject to the XSOC Lic
top.v
module top(q, a, b, sel, r_l, clk, rst);
output [7:0] q;
input [7:0] a, b;
input sel, r_l, clk, rst;
wire [7:0] mux_out, reg_out;
mux mux_1 (.outvec(mux_out), .a_vec(a), .b_vec(b), .sel(sel));
mux.v
module mux (outvec, a_vec, b_vec, sel);
output[7:0] outvec;
input[7:0] a_vec, b_vec;
input sel;
mux21 u0 (.Y(outvec[0]), .A(a_vec[0]), .B(b_vec[0]), .SEL(sel));
mux21 u1 (.Y(outvec[1]), .A(a_ve
rotate.v
module rotate(q, data, clk, r_l, rst); // rotates bits or loads
output [7:0] q;
input [7:0] data;
input clk, r_l, rst;
reg [7:0] q;
// when r_l is high, it rotates; if low, it loads data
alway
v.h
/****************************************************************************
*
* Open Watcom Project
*
* Portions Copyright (c) 1983-2002 Sybase, Inc. All Rights Res
v.h
/****************************************************************************
*
* Open Watcom Project
*
* Portions Copyright (c) 1983-2002 Sybase, Inc. All Rights Res
timescale.v
`timescale 1ns / 10ps
disp.v
//
// decoder for 7 led display
//
module disp (in, out);
input [7:0] in;
output [13:0] out;
reg [13:0] out;
always @(in)
begin
case (in[7:4])
4'h0: out[13:7] = 7'b1110111;