picoblaze_hc164.v

Xilinx ISE9.x FPGACPLD设计指南 原书光盘上的源码 包含大量vhdl源码

module picoblaze_hc164(
  iCLK,
  iRST_N,
  iADDR,
  iDATAIN,
  iWR,
  iRD,
    
  oHC_DBUS,
 
  oHCCP,
  oHCSI
);

parameter C_BASEADDR = 8'h00;

input         iCLK     ;  // OPB Bus clock
input         iRST_N   ;  // System RST Low Active
input [ 7: 0] iADDR    ;  // Address Bus 32 bits
input [ 7: 0] iDATAIN  ;  // Data Bus input 32 bits

input         iWR      ;
input         iRD      ;
 
output[ 7: 0] oHC_DBUS ;  // Data Bus output 32bits
                          
output        oHCCP    ;  // Enable Clock Signal to HC164 chip
output        oHCSI    ;  // Serial Data transfer to HC164 chip


wire [ 3: 0] s_LED_VAL;
wire [15: 0] s_SEG_VAL;
wire [ 3: 0] s_SEG_DOT;

hc164_driver hc164_driver_inst(
    .clk(           iCLK),
    .rst_n(       iRST_N),
    .led(      s_LED_VAL),
    .seg_value(s_SEG_VAL),
    .dot(      s_SEG_DOT),
    .hc_si(        oHCSI),
    .hc_cp(        oHCCP)
);

picoblaze_hc164_busif #(.C_BASEADDR( C_BASEADDR ) )busif(
  .iCLK(         iCLK),
  .iRST_N(     iRST_N),
  .iADDR(       iADDR),
  .iDATAIN(   iDATAIN),
  .iWR(           iWR),
  .iRD(           iRD),        
  .oHC_DBUS( oHC_DBUS),
  .oLED_VAL(s_LED_VAL),
  .oSEG_VAL(s_SEG_VAL),
  .oSEG_DOT(s_SEG_DOT)
);
endmodule