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V 的代码
v.c
main (int *p)
{
int a;
a = 0;
p[1] = a;
a = 0;
p[2] = a;
a = 123456;
p[3] = a;
}
timescale.v
`timescale 1ns / 10ps
lfsr.v
/////////////////////////////////////////////////////////////////////
//// ////
//// Linear Feedback Shift Register
gb-v
%!PS-Adobe-3.0 Resource-CMap
%%DocumentNeededResources: ProcSet (CIDInit)
%%DocumentNeededResources: CMap (GB-H)
%%IncludeResource: ProcSet (CIDInit)
%%IncludeResource: CMap (GB-H)
%%BeginResource: CM
gbt-v
%!PS-Adobe-3.0 Resource-CMap
%%DocumentNeededResources: ProcSet (CIDInit)
%%DocumentNeededResources: CMap (GBT-H)
%%IncludeResource: ProcSet (CIDInit)
%%IncludeResource: CMap (GBT-H)
%%BeginResource:
mydcm.v
// Module MyDCM
// Generated by Xilinx Architecture Wizard
// Verilog
// Written for synthesis tool: XST
// Xilinx device: xc2v40-4fg256
module MyDCM(LOCKED_OUT, CLKIN_IN, CLK2X_OUT, CLK0_OUT);
mydcm.v
// Module MyDCM
// Generated by Xilinx Architecture Wizard
// Verilog
// Written for synthesis tool: XST
// Xilinx device: xc2v40-4fg256
module MyDCM(LOCKED_OUT, CLKIN_IN, CLK2X_OUT, CLK0_OUT);
timescale.v
`timescale 1ps/1ps
or1200_if.v
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's instruction fetch
fail.v
// ________________________________________________________________ fail.v ___
`timescale 1ns/100ps
module testit(input logic PCLK, input logic psel, input logic PENABLE);
always @(pose