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clock.v
module clock_gen (clock);
parameter Half_cycle = 50;
output clock;
reg clock;
initial
clock = 0;
always
begin
# Half_cycle clock = ~ clock;
end
endmodule
nrzi.v
module NRZI_Mealy (B_out, B_in, clk, rst);
output B_out;
input B_in, clk, rst;
reg [2: 0] state, next_state;
reg B_out;
parameter S_0 = 0;
parameter S_1 = 1;
parameter S_2 = 2;
parameter
or_nand.v
module or_nand (y, enable, x1, x2, x3, x4);
output y;
input enable, x1, x2, x3, x4;
assign y = ~(enable & (x1 | x2) & (x3 | x4));
endmodule
nrzi.v
vti_encoding:SR|utf8-nl
vti_timelastmodified:TR|08 Dec 2001 19:58:52 -0000
vti_extenderversion:SR|5.0.2.4330
vti_lineageid:SR|{68196FE4-025E-448D-B7A4-83D0C37BB7BA}
vti_cacheddtm:TX|08 Dec 2001 19
or_nand.v
vti_encoding:SR|utf8-nl
vti_timelastmodified:TR|12 Jun 2002 17:24:12 -0000
vti_extenderversion:SR|5.0.2.4330
vti_lineageid:SR|{882B7905-0F22-48A5-999C-A2A1B4B2DCC6}
vti_cacheddtm:TX|12 Jun 2002 17
fifo.v
vti_encoding:SR|utf8-nl
vti_timelastmodified:TR|13 Jun 2002 00:56:06 -0000
vti_extenderversion:SR|5.0.2.4330
vti_lineageid:SR|{02B126E0-1CF0-4891-BC9D-57E1FBD18AE4}
vti_cacheddtm:TX|13 Jun 2002 00
fifo.v
// M.D. Ciletti 4-4-2001
// Note: Adjust stack parameters
// Note: Model does not support simultaneous read and write, and would need
// additional logic.
// As written, ptr-diff would have two n
disp.v
//
// decoder for 7 led display
//
module disp (in, out);
input [7:0] in;
output [13:0] out;
reg [13:0] out;
always @(in)
begin
case (in[7:4])
4'h0: out[13:7] = 7
v0.90
086726cd8b2363884527c1a02423bf8cac7a23f1
v1.20
34b94b4519a301ee88d03c763c58f45f30605f52