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asmi.v
//Legal Notice: (C)2005 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic function
sysid.v
//Legal Notice: (C)2005 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic function
dcr_if.v
//----------------------------------------------------------------------------
// DCR_IF Controller - DCR Bus Interface
//----------------------------------------------------------------------------
plb_if.v
//----------------------------------------------------------------------------
// PLB INTERFACE - Sub Level Module
//-----------------------------------------------------------------------------
//
tft_if.v
//----------------------------------------------------------------------------
// TFT INTERFACE - Sub Level Module
//-----------------------------------------------------------------------------
//
dcr_if.v
//----------------------------------------------------------------------------
// DCR_IF Controller - DCR Bus Interface
//----------------------------------------------------------------------------
plb_if.v
//----------------------------------------------------------------------------
// PLB INTERFACE - Sub Level Module
//-----------------------------------------------------------------------------
//
tft_if.v
//----------------------------------------------------------------------------
// TFT INTERFACE - Sub Level Module
//-----------------------------------------------------------------------------
//
decoder.v
module decoder (Data, Code);
output [7: 0] Data;
input [2: 0] Code;
reg [7: 0] Data;
always @ (Code)
begin
if (Code == 0) Data = 8'b00000001; else
if (Code == 1
comparator.v
module comparator (a_gt_b, a_lt_b, a_eq_b, a, b); // Alternative algorithm
parameter size = 2;
output a_gt_b, a_lt_b, a_eq_b;
input [size: 1] a, b;
reg a_gt_b, a_lt_b, a_eq_b;