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vregsw.v
//////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2007 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
////
lcd.v
module lcd(clk,rst,data_in,lcd_e,lcd_rw,lcd_rs,data);
input clk,rst;
input [7:0] data_in;
output lcd_e,lcd_rw,lcd_rs;
output [7:0] data;
reg lcd_e,lcd_rw,lcd_rs;
reg [7:0] data,data_in_buf
top.v
module top(q, a, b, sel, r_l, clk, rst);
output [7:0] q;
input [7:0] a, b;
input sel, r_l, clk, rst;
wire [7:0] mux_out, reg_out;
mux mux_1 (.outvec(mux_out), .a_vec(a), .b_vec(b), .sel(sel));
mux.v
module mux (outvec, a_vec, b_vec, sel);
output[7:0] outvec;
input[7:0] a_vec, b_vec;
input sel;
mux21 u0 (.Y(outvec[0]), .A(a_vec[0]), .B(b_vec[0]), .SEL(sel));
mux21 u1 (.Y(outvec[1]), .A(a_ve
rotate.v
module rotate(q, data, clk, r_l, rst); // rotates bits or loads
output [7:0] q;
input [7:0] data;
input clk, r_l, rst;
reg [7:0] q;
// when r_l is high, it rotates; if low, it loads data
alway
top.v
module top(q, a, b, sel, r_l, clk, rst);
output [7:0] q;
input [7:0] a, b;
input sel, r_l, clk, rst;
wire [7:0] mux_out, reg_out;
mux mux_1 (.outvec(mux_out), .a_vec(a), .b_vec(b), .sel(sel));
mux.v
module mux (outvec, a_vec, b_vec, sel);
output[7:0] outvec;
input[7:0] a_vec, b_vec;
input sel;
mux21 u0 (.Y(outvec[0]), .A(a_vec[0]), .B(b_vec[0]), .SEL(sel));
mux21 u1 (.Y(outvec[1]), .A(a_ve
rotate.v
module rotate(q, data, clk, r_l, rst); // rotates bits or loads
output [7:0] q;
input [7:0] data;
input clk, r_l, rst;
reg [7:0] q;
// when r_l is high, it rotates; if low, it loads data
alway
alu.v
module alu(clk, a, b, opcode, outp);
input clk;
input [7:0] a, b;
input [2:0] opcode;
output [7:0] outp;
reg [7:0] outp;
always @(posedge clk)
begin
case (opcode) /* synthesis full_c
asmi.v
//Legal Notice: (C)2005 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic function