vregsw.v

verilog语言 vga 控制 和显示功能

//////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2007 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
//////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /   Vendor:        Xilinx
// \   \   \/    Version:       1.0.0
//  \   \        Filename:      vregsw.v
//  /   /        Date Created:  July 1, 2007
// /___/   /\    Last Modified: July 1, 2007
// \   \  /  \
//  \___\/\___\
//
// Devices:   Spartan-3 Generation FPGA
// Purpose:   Executable PicoBlaze code from vregsw.psm without JTAG Loader
// Contact:   [e-mail]
// Reference: None
//
// Revision History:
//   Rev 1.0.0 - (crabill) First created July 1, 2007.
//
//////////////////////////////////////////////////////////////////////////////
//
// LIMITED WARRANTY AND DISCLAIMER. These designs are provided to you "as is".
// Xilinx and its licensors make and you receive no warranties or conditions,
// express, implied, statutory or otherwise, and Xilinx specifically disclaims
// any implied warranties of merchantability, non-infringement, or fitness for
// a particular purpose. Xilinx does not warrant that the functions contained
// in these designs will meet your requirements, or that the operation of
// these designs will be uninterrupted or error free, or that defects in the
// designs will be corrected. Furthermore, Xilinx does not warrant or make any
// representations regarding use or the results of the use of the designs in
// terms of correctness, accuracy, reliability, or otherwise.
//
// LIMITATION OF LIABILITY. In no event will Xilinx or its licensors be liable
// for any loss of data, lost profits, cost or procurement of substitute goods
// or services, or for any special, incidental, consequential, or indirect
// damages arising from the use or operation of the designs or accompanying
// documentation, however caused and on any theory of liability. This
// limitation will apply even if Xilinx has been advised of the possibility
// of such damage. This limitation shall apply not-withstanding the failure
// of the essential purpose of any limited remedies herein.
//
//////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2007 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, All Rights Reserved.
//////////////////////////////////////////////////////////////////////////////
 
`timescale 1 ns / 1 ps
 
module vregsw
  (
  input  wire  [9:0] address,
  input  wire        clk,
  output wire [17:0] instruction
  );
 
  RAMB16_S18 #(
    .INIT_00(256'h103340331033403210334031015D0175009FE0030039E0020001E001000002DE),
    .INIT_01(256'h1088402D1081402B106440501033403810334037103340361033403510334034),
    .INIT_02(256'h10D6405810D1405A10CC404410C7405310C2404110BD404510B8405710B34051),
    .INIT_03(256'hA0036001403EE1020102403EE1020101403B50382004E001C031400910DB4043),
    .INIT_04(256'h00640052E1030111504D40030129504D40020123504D4001013A504D40000139),
    .INIT_05(256'h4206120442051200420411FC420311F8420211F4420111F042006201A0000000),
    .INIT_06(256'hC4186402A00000000158000D0158000D01621020006E0261A000120C42071208),
    .INIT_07(256'h02A802EB02F70317031402FD02C102E4031402FD1240031402FD02C002E46403),
    .INIT_08(256'h6402A00000000064008FC5011520006EA00000000064008F85011520006EA000),
    .INIT_09(256'h0401A00002A802EB031402FD1250031402FD1240031402FD02C002E46403C418),
    .INIT_0A(256'h031402FD0211031402FD0220031402FD02C002E4A00000A6C418040200A6C418),
    .INIT_0B(256'h029B013A0104A0000000029B01280104A0000000029B01160104A00002A802EB),
    .INIT_0C(256'h0000029B013A00F2A0000000029B012800F2A0000000029B011600F2A0000000),
    .INIT_0D(256'hA0000000029B013A00E0A0000000029B012800E0A0000000029B011600E0A000),
    .INIT_0E(256'h028502A8014C05170429014C05080423014C0508043A014C05150439C4180401),
    .INIT_0F(256'h014C05170429014C05090423014C0508043A014C05170439C4180401A000026E),
    .INIT_10(256'h0429014C050A0423014C0508043A014C05190439C4180401A0000275028502A8),
    .INIT_11(256'h05020423014C0507043A014C05170439C4180402A000027E028502A8014C0517),
    .INIT_12(256'h014C0508043A014C05170439C4180402A000026E029002A8014C05080429014C),
    .INIT_13(256'h043A014C05170439C4180402A0000275029002A8014C05090429014C05030423),
    .INIT_14(256'h031402FD02C002E4A000027E029002A8014C050A0429014C05040423014C0509),
    .INIT_15(256'h515D21014102A000C000555821014101A00002EB031402FD1250031402FD1240),
    .INIT_16(256'h5971C00AA00F10200158803A8007596AC00A000E000E000E000E1200A0004000),
    .INIT_17(256'h003201580053015800520158000D0158000D0158000DA00010200158803A8007),
    .INIT_18(256'h0020015800470158004501580052015800560158002001580032015800330158),
    .INIT_19(256'h000D0158006C0158006F01580072015800740158006E0158006F015800430158),
    .INIT_1A(256'h003A015800470158004E015800490158004E0158005201580041015800570158),
    .INIT_1B(256'h0045015800500158004F01580052015800500158004D01580049015800200158),
    .INIT_1C(256'h00410158004D0158002001580045015800530158005501580020015800520158),
    .INIT_1D(256'h004501580047015800410158004D015800410158004401580020015800590158),
    .INIT_1E(256'hA0000158000D0158000D01580021015800420158004301580050015800200158),
    .INIT_1F(256'hA000024E02450210A000024E023C0210A000024E02310210A000024E02260210),
    .INIT_20(256'hA000024E0245021BA000024E023C021BA000024E0231021BA000024E0226021B),
    .INIT_21(256'h00470158004501580052A0000158002001580031015800470158004501580052),
    .INIT_22(256'h01580020015800310158004F015800440158004CA00001580020015800320158),
    .INIT_23(256'h0158005701580053A00001580020015800320158004F015800440158004CA000),
    .INIT_24(256'h01580053A00001580020015800320158005701580053A0000158002001580031),
    .INIT_25(256'h0158000D01580064015800650158007401580063015800650158006C01580065),
    .INIT_26(256'h0158004CA000015800200158003D01580020015800670158006501580052A000),
    .INIT_27(256'h01580048A000015800200158004D0158004F0158004EA000015800200158004F),
    .INIT_28(256'hA0000158002001580041015800470158005001580046A0000158002001580049),
    .INIT_29(256'h00730158006501580054A0000158002001580032015800520158004401580044),
    .INIT_2A(256'hC0180002A000C0180001A000C0180000A0000158000D0158000D015800740158),
    .INIT_2B(256'h6000A000E000C0026000A00002B102B102B102B102B1A00056B2C001000BA000),
    .INIT_2C(256'h02CB02BFA000C0196000A000E000A0FE6000A000E000C0016000A000E000A0FD),
    .INIT_2D(256'hE0000003A00052DA2001401902CB02C3A00002B502CB02C7A00002CB02BBA000),
    .INIT_2E(256'h02D102B602D802B502CEA00002D402B602CE02B502D802D1A000C0180000C019),
    .INIT_2F(256'h570232100180A00002D402B602D802B502D1A00002D402B602D802B502CEA000),
    .INIT_30(256'h411902B102B102D802B502D142FEB800010E02D402B602D802B502D1430302CE),
    .INIT_31(256'h000000004318B800030E02002102030A0380A0002102030AA00002D402B102B1),
    .INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
    .INITP_00(256'hFFF3F3CC88CCCFB777777748F8D34D340E38F67DDDDDDDDDDDDDDDDDDDDFE223),
    .INITP_01(256'hC30C308BFC30C3088FE3F8FE3F8FE3F8FE3F8FEFF3CF3B8E2FF3CF3223D38F4E),
    .INITP_02(256'h33333235D0D76A88D2B4BF3CF3BFC30C308BFC30C308BFC30C308BFC30C308BF),
    .INITP_03(256'hBFBFBFBFB3333333333333333333333333333333333333333333333333333333),
    .INITP_04(256'hCB3332CCCB333332CCCCCCCCCB3332CCCCB33332CCCCCB33332CCCCCBFBFBFBF),
    .INITP_05(256'hD2FFEFFEFFEFFFA28B4FBFBEFA282828282FFED28A28B333332CCCCCB33332CC),
    .INITP_06(256'h0000000000000000000000000000000000000000000000000EA727BF3FFEBFFF),
    .INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000))
  ram_1024_x_18 (
    .DI(16'h0000),
    .DIP(2'b00),
    .EN(1'b1),
    .WE(1'b0),
    .SSR(1'b0),
    .CLK(clk),
    .ADDR(address),
    .DO(instruction[15:0]),
    .DOP(instruction[17:16]));
 
endmodule