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sysid.v
//Legal Notice: (C)2005 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic function
asmi.v
//Legal Notice: (C)2005 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic function
sysid.v
//Legal Notice: (C)2005 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic function
asmi.v
//Legal Notice: (C)2005 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic function
sysid.v
//Legal Notice: (C)2005 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic function
excalibur.v
// megafunction wizard: %ARM-Based Excalibur%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ARM-Based Excalibur
// PROJECT: excalibur
// ========================================================
setpw.v
module setpw(cfm,DATA,DOUT,again,mis);
input cfm;
input[23:0] DATA;
output[23:0] DOUT;
output again,mis;
reg[23:0] DOUT;
reg again,mis;
reg[23:0] a;
reg i;
always @(posedge cfm)
begin
if
setpw.v
module setpw(cfm,DATA,DOUT,again,mis,ok);
input cfm;
input[23:0] DATA;
output[23:0] DOUT;
output again,mis,ok;
reg[23:0] DOUT;
reg again,mis;
reg[23:0] a;
reg i,ok;
always @(posedge cfm)
be
tellpw.v
module tellpw(DIN,DATA,cfm,ok,n,lock,mis);
input[23:0] DIN,DATA;
input cfm;
output ok,lock,mis;
output[1:0] n;
reg ok,lock,mis;
reg[1:0] n;
always @(posedge cfm)
begin
if(DIN==DATA)
be
keyvalue.v
module KEYVALUE(clk,d,dout);
input clk;
input[7:0] d;
output[3:0] dout;
reg[3:0] dout;
always @(posedge clk)
begin
case(d)
8'b1000_1000: dout=4'b0000;
8'b1000_0100: dout=4'b0001;
8'