setpw.v

是一些很好的FPGA设计实例

module setpw(cfm,DATA,DOUT,again,mis,ok);
input cfm;
input[23:0] DATA;
output[23:0] DOUT;
output again,mis,ok;
reg[23:0] DOUT;
reg again,mis;
reg[23:0] a;
reg i,ok;
always @(posedge cfm)
 begin
  if(i==0)
   begin
   a=DATA;
   again=1;
   mis=0;
   i=1;
   ok=0;
   end
  else if(a==DATA)
   begin
   DOUT=DATA;
   again=0;
   mis=0;
   i=0;
   ok=1;
   end
  else
   begin
   mis=1;
   again=0;
   i=0;
   ok=0;
   end
 end
endmodule