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verilog.v
// generated by newgenasym Fri Mar 16 11:23:24 2001
module cap_np (a, b);
inout a;
inout b;
initial
begin
end
endmodule
verilog.v
// generated by genview Wed Apr 15 08:26:06 1998
module blockout (a);
inout a;
initial
begin
end
endmodule
verilog.v
// generated by newgenasym Fri Mar 16 11:23:04 2001
module cap (a, b);
inout a;
inout b;
initial
begin
end
endmodule
verilog.v
// generated by newgenasym Fri Mar 16 12:55:13 2001
module photo_diode (anode, cathode);
inout anode;
inout cathode;
initial
begin
end
endmodule
verilog.v
// generated by NetAssembler Version 14.00-p003 Oct 18th, 2000 12:00:00 IST
// on Tue Mar 20 15:11:47 2001
`timescale 1ns/1ns
`define scale_fs * 0.000001000000000
`define scale_ps * 0.001000000000
verilog.v
// generated by newgenasym Tue Mar 20 14:39:52 2001
module data (gain, outa, outb, vclka, vclkc, vd);
input gain;
output outa;
output outb;
input vclka;
input vclkc;
input [
verilog.v
`timescale 1ns/1ns
module data (outa, outb, gain, vclka, vclkc, vd );
// generated by HDL Direct 14.20-p006 14-Mar-2002
// on Wed May 01 09:04:34 2002
// from project1_lib/DATA/sch_1
output outa
verilog.v
// generated by newgenasym Thu Mar 22 13:53:53 2001
module daamp (dq0, dq1, dq2, dq3, dq4, dq5, dq6, dq7, gain, out, vclk, vref);
input dq0;
input dq1;
input dq2;
input dq3;
inp
verilog.v
`timescale 1ns/1ns
module daamp (out, dq0, dq1, dq2, dq3, dq4, dq5, dq6, dq7, gain, vclk, vref );
// generated by HDL Direct 14.20-p006 14-Mar-2002
// on Wed May 01 09:04:35 2002
// from project1_li
verilog.v
`timescale 1ns/1ns
module root ();
// generated by HDL Direct 14.20-p006 14-Mar-2002
// on Wed May 01 09:04:32 2002
// from project1_lib/ROOT/sch_1
// global signal glbl.agnd;
// global signal