源码文件
/* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that …
cpld 源代码
CPLD采用CMOSEPROM、EEPROM、快闪存储器和SRAM等编程技术，从而构成了高密度、高速度和低功耗的可编程逻辑器件。cPCI总线
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源码文件
library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use IEEE.std_logic_arith.all; entity fpdpsk is …
源码文件
--updown (of testup) library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;…
源码文件
-- Copyright (C) 1988-2002 Altera Corporation -- Any megafunction design, and related net list (encrypted or decrypted), -- supp…
源码文件
/* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that …
源码文件
test_inst : test PORT MAP( address => address_sig, inclock => inclock_sig, outclock => outclock_sig, q => q_sig …
源码文件
--dirve library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use IEEE.std_logic_arith.all; entity …
源码文件
--SEL2 模块 library ieee; use ieee.std_logic_1164.all; entity sel2 is port( kin1,kin2: in std_logic; sel:in std_logi…
源码文件
--addr (模块)正弦 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity addr is port( clk:in s…
源码文件
--dis_sig library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity dis_sig is port( key:in std_logic…