源码文件
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; LIBRARY lpm; USE lp…
cpld 源代码
CPLD采用CMOSEPROM、EEPROM、快闪存储器和SRAM等编程技术，从而构成了高密度、高速度和低功耗的可编程逻辑器件。cPCI总线
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源码文件
DEPTH = 256; % Memory depth and width are required % WIDTH = 8; % Enter a decimal number % ADDRESS_RADIX = HEX; % Address and …
源码文件
源码文件
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; PACKAGE ram_constant…
源码文件
--2选1电路方法1 --library ieee; --use ieee.std_logic_1164.all; --entity mux2_1 is --port(d0,d1,sel:in std_logic; …
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Library IEEE ; use IEEE.std_logic_1164.all ; ENTITY reg4 IS PORT( d:in std_logic_vector(3 downto 0); ci: IN std_logi…
源码文件
library ieee; use ieee.std_logic_1164.all; entity or2a is port ( a: in bit ; b: in bit ; c: out bit); end or2a; architectu…
源码文件
/* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that …
源码文件
/* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that …
源码文件
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity adder4bit is port(cin:in std_logic; …