源码文件
Library IEEE ; use IEEE.std_logic_1164.all ; ENTITY reg8 IS PORT( d_1:in std_logic_vector(3 downto 0); d_2:in std_lo…
cpld 源代码
CPLD采用CMOSEPROM、EEPROM、快闪存储器和SRAM等编程技术，从而构成了高密度、高速度和低功耗的可编程逻辑器件。cPCI总线
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源码文件
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; package dp16 is fu…
源码文件
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity mul16 is po…
源码文件
Library IEEE ; use IEEE.std_logic_1164.all ; ENTITY reg4_1 is PORT(d:in std_logic_vector(3 downto 0); clk : IN std_l…
源码文件
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity mydivider is …
源码文件
/* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that …
源码文件
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity mul_8 is --接口 port(clk:in std_logi…
源码文件
library ieee; use ieee.std_logic_1164.all; entity f_adder IS port (ain,bin,cin : IN STD_LOGIC; cout,sum : OUT …
源码文件
/* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that …
源码文件
/* WARNING: Do NOT edit the input and output ports in this file in a text editor if you plan to continue editing the block that …