源码文件
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY mux IS port(s:in std_logic_vector(2 down…
VHDL-AMS 源代码
VHDL-AMS是VHDL的一个分支，它支持模拟、数字、数模混合电路系统的建模与仿真。
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源码文件
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; ENTITY mux IS port(s:in std_logic_vector(2 down…
源码文件
-- This is the VHDL code for the counter example from _The VHDL -- Cookbook_ by Peter Ashenden. The propogation delay has been r…
源码文件
-- This is the VHDL code for the counter example from _The VHDL -- Cookbook_ by Peter Ashenden. The propogation delay has been r…
源码文件
--Entity declaration for 4:1 Mux ENTITY mux41 is port( d0, d1, d2, d3 : in bit_vector; s0, s1, en : in bit; z : out bit_vecto…
源码文件
--Entity declaration for 4:1 Mux ENTITY mux41 is port( d0, d1, d2, d3 : in bit_vector; s0, s1, en : in bit; z : out bit_vecto…
源码文件
library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all; entity counter is port(C, CLR : in std_logic; …
源码文件
library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all; entity counter is port(C, CLR : in std_logic; …
源码文件
library IEEE; use IEEE.STD_LOGIC_1164.all; entity HA is port(A,B:in STD_LOGIC; Sum, Carry:out STD_LOGIC); end HA; architectur…
源码文件
library IEEE; use IEEE.STD_LOGIC_1164.all; entity HA is port(A,B:in STD_LOGIC; Sum, Carry:out STD_LOGIC); end HA; architectur…