vhdl code6.bak

d flip flop t flip flop counter mux using active hdl can be run using 3.2 version and creating new d

--Entity declaration for 4:1 Mux 
ENTITY mux41 is
port( d0, d1, d2, d3 : in bit_vector;
s0, s1, en : in bit;
z : out bit_vector);
END ENTITY mux41;

--Architecture for 4:1 Mux
ARCHITECTURE beh OF mux41 IS
BEGIN
driver : PROCESS IS

BEGIN
--The logic for the output of the mux
if s0 = '0' and s1 = '0' then
z <= d0;
end if;
if s0 = '1' and s1 = '0' then
z <= d1;
end if;
if s0 = '0' and s1 = '1' then
z <= d2;
end if;
if s0 = '1' and s1 = '1' then
z <= d3;
end if;

WAIT ON s0, s1;

END PROCESS driver;
END ARCHITECTURE beh;

--TESTING PROBLEM 1

ENTITY test_bench IS
END ENTITY test_bench;
ARCHITECTURE test_mux41 of test_bench IS

--Declaration of the signals, give the bit vectors a size
signal d0, d1, d2, d3, z : bit_vector(3 downto 0);
signal s0, s1, en : bit;
BEGIN
dut : ENTITY work.mux41(beh)
PORT MAP ( d0, d1, d2, d3, s0, s1, en, z );
driver : PROCESS IS
BEGIN
s0 <= '0'; s1 <= '0';
d0 <= x"0"; d1 <= X"1"; d2 <= x"1"; d3 <= x"1"; en <= '1';
WAIT FOR 20 ns;
s0 <= '1'; s1 <= '1';
WAIT FOR 20 ns;
WAIT;
END PROCESS driver;
END ARCHITECTURE test_mux41;