vhdl code7.bak

来自「d flip flop t flip flop counter mux usin」· BAK 代码 · 共 28 行

LIBRARY ieee; 
USE ieee.std_logic_1164.all; 
USE ieee.std_logic_arith.all; 

ENTITY mux IS 
port(s:in std_logic_vector(2 downto 0); 
inp:in std_logic_vector(7 downto 0); 
op: out std_logic); 
END ENTITY mux; 

-- 
ARCHITECTURE mux OF mux IS 
BEGIN 
process(s,inp) 
begin 
case s is 
when "000"=>op<=inp(0); 
when "001"=>op<=inp(1); 
when "010"=>op<=inp(2); 
when "011"=>op<=inp(3); 
when "100"=>op<=inp(4); 
when "101"=>op<=inp(5); 
when "110"=>op<=inp(6); 
when others=>op<=inp(7); 
end case; 
end process; 
END ARCHITECTURE mux;