ABSTRACTThe flyback power stage is a popular choice for single and multiple output dc-to-dc converters at powerlevels of 150 Watts or less. Without the output inductor required in buck derived topologies, such as theforward or push-pull converter, the component count and cost are reduced. This application note will reviewthe design procedure for the power stage and control electronics of a flyback converter. In these isolatedconverters, the error signal from the secondary still needs to cross the isolation boundary to achieveregulation. By using the UC3965 Precision Reference with Low Offset Error Amplifier on the secondaryside to drive an optocoupler and the UCC3809 Economy Primary Side Controller on the primary side, asimple and low cost 50 Watt isolated power supply is realized.
标签： 隔离
上传时间： 2021-11-24
上传用户：kingwide
General Design Specification:1. AC Input Range 180-264Vac, Isolated ac-dc offline, 12LEDS,Output 700mA2. Intelligent wall dimmer detections(Leading-edge dimmer , Trailing-edgedimmer , No-dimmer)3. Multiple dimming control scheme4. Wide dimming range from 1% up to 100%5. No visible flicker6. Resonant control to achieve high efficiency7. High Power Factor, 0.9 without dimmer8. Temperature degrade control to adjust the LED9. Primary-only Sensing eliminates opto-isolator feedback and simplifies design
标签： iw3617
上传时间： 2021-12-03
上传用户：canderile
AT89C51设计LCD1602显示DS1302实时日历时钟毕业论文文档+软件源码,单片机LCD毕业设计，有代码、仿真电路、设计报告,仿真使用的是proteus仿真，可直接加载HEX文件运行. 此次设计的要求是通过LCD与单片机的连接模块能够显示数字（如时间）、字符（如英文）和图形等，这就需要专门的时钟芯片-----DS1302。 DS1302是一种高性能、低功耗、带RAM的实时时钟芯片，它能够对时，分，秒进行精确计时，它与单片机的接口使用同步串行通信，仅用3条线与之相连接，就可以实现MCS-51单片机对其进行读写操作，把读出的时间数据送到LCD1602上显示。程序运行时，必须先对LM044L进行初始设置，然后，通过单片机从DS1302中获取时间并通过LCD1602显示。同时，进行循环赋值，使LCD动态显示当前的时间。关键字：AT89C51、DS1302，LCD1602显示器 一．设计任务和要求 1. 利用DS1302实现年月日时分秒，并用LCD显示。2. 通过LCD模块与单片机的接口，能显示数字（如时间）、字符（如英文）。3. 硬件设计部分，根据设计的任务选定合适的单片机，根据控制对象设计接口电路。设计的单元电路必须有工作原理,器件的作用,分析和计算过程；4. 软件设计部分，根据电路工作过程，画出软件流程图，根据流程图编写相应的程序，进行调试并打印程序清单；5.原理图设计部分，根据所确定的设计电路，利用Proteus工具软件绘制电路原理图。6计算说明书部分包括方案论证报告打印版或手写版，程序流程图具体程序等7. 图纸部分包括具体电路原理图打印版8. 设计要求还包括利用一天时间进行资料查阅与学习讨论，利用5天时间在实验室进行分散设计，最后三天编写报告。最后一天进行成果验收。
上传时间： 2021-12-08
上传用户：
FPGA读取OV5640摄像头数据并通过VGA或LCD屏显示输出的Verilog逻辑源码Quartus工程文件+文档说明，FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。module top( input clk, input rst_n, output cmos_scl, //cmos i2c clock inout cmos_sda, //cmos i2c data input cmos_vsync, //cmos vsync input cmos_href, //cmos hsync refrence,data valid input cmos_pclk, //cmos pxiel clock output cmos_xclk, //cmos externl clock input [7:0] cmos_db, //cmos data output cmos_rst_n, //cmos reset output cmos_pwdn, //cmos power down output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b, //vga blue output sdram_clk, //sdram clock output sdram_cke, //sdram clock enable output sdram_cs_n, //sdram chip select output sdram_we_n, //sdram write enable output sdram_cas_n, //sdram column address strobe output sdram_ras_n, //sdram row address strobe output[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank address output[12:0] sdram_addr, //sdram address inout[15:0] sdram_dq //sdram data);
上传时间： 2021-12-18
上传用户：
基于FPGA设计的字符VGA LCD显示实验Verilog逻辑源码Quartus工程文件+文档说明,通过字符转换工具将字符转换为 8 进制 mif 文件存放到单端口的 ROM IP 核中，再从ROM 中把转换后的数据读取出来显示到 VGA 上，FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。module top( input clk, input rst_n, //vga output output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b //vga blue );wire video_clk;wire video_hs;wire video_vs;wire video_de;wire[7:0] video_r;wire[7:0] video_g;wire[7:0] video_b;wire osd_hs;wire osd_vs;wire osd_de;wire[7:0] osd_r;wire[7:0] osd_g;wire[7:0] osd_b;assign vga_out_hs = osd_hs;assign vga_out_vs = osd_vs;assign vga_out_r = osd_r[7:3]; //discard low bit dataassign vga_out_g = osd_g[7:2]; //discard low bit dataassign vga_out_b = osd_b[7:3]; //discard low bit data//generate video pixel clockvideo_pll video_pll_m0( .inclk0 (clk ), .c0 (video_clk ));color_bar color_bar_m0( .clk (video_clk ), .rst (~rst_n ), .hs (video_hs ), .vs (video_vs ), .de (video_de ), .rgb_r (video_r ), .rgb_g (video_g ), .rgb_b (video_b ));osd_display osd_display_m0( .rst_n (rst_n ), .pclk (video_clk ), .i_hs (video_hs ), .i_vs (video_vs ), .i_de (video_de ), .i_data ({video_r,video_g,video_b} ), .o_hs (osd_hs ), .o_vs (osd_vs ), .o_de (osd_de ), .o_data ({osd_r,osd_g,osd_b} ));endmodule
上传时间： 2021-12-18
上传用户：
基于FPGA设计的sdram读写测试实验Verilog逻辑源码Quartus工程文件+文档说明，DRAM选用海力士公司的 HY57V2562 型号,容量为的 256Mbit,采用了 54 引脚的TSOP 封装, 数据宽度都为 16 位, 工作电压为 3.3V,并丏采用同步接口方式所有的信号都是时钟信号。FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。timescale 1ps/1psmodule top(input clk,input rst_n,output[1:0] led,output sdram_clk, //sdram clockoutput sdram_cke, //sdram clock enableoutput sdram_cs_n, //sdram chip selectoutput sdram_we_n, //sdram write enableoutput sdram_cas_n, //sdram column address strobeoutput sdram_ras_n, //sdram row address strobeoutput[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank addressoutput[12:0] sdram_addr, //sdram addressinout[15:0] sdram_dq //sdram data);parameter MEM_DATA_BITS = 16 ; //external memory user interface data widthparameter ADDR_BITS = 24 ; //external memory user interface address widthparameter BUSRT_BITS = 10 ; //external memory user interface burst widthparameter BURST_SIZE = 128 ; //burst sizewire wr_burst_data_req; // from external memory controller,write data request ,before data 1 clockwire wr_burst_finish; // from external memory controller,burst write finish
标签： fpga sdram verilog quartus
上传时间： 2021-12-18
上传用户：
基于FPGA设计的vga显示测试实验Verilog逻辑源码Quartus工程文件+文档说明，FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。module top( input clk, input rst_n, //vga output output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b //vga blue );wire video_clk;wire video_hs;wire video_vs;wire video_de;wire[7:0] video_r;wire[7:0] video_g;wire[7:0] video_b;assign vga_out_hs = video_hs;assign vga_out_vs = video_vs;assign vga_out_r = video_r[7:3]; //discard low bit dataassign vga_out_g = video_g[7:2]; //discard low bit dataassign vga_out_b = video_b[7:3]; //discard low bit data//generate video pixel clockvideo_pll video_pll_m0( .inclk0(clk), .c0(video_clk));color_bar color_bar_m0( .clk(video_clk), .rst(~rst_n), .hs(video_hs), .vs(video_vs), .de(video_de), .rgb_r(video_r), .rgb_g(video_g), .rgb_b(video_b));endmodule
标签： fpga vga显示 verilog quartus
上传时间： 2021-12-19
上传用户：kingwide
Texas instruments MIPI DSI to eDP converter. Input supports 2 channel, 4 lanes each, up to 1.5GBit/s. Total input bandwidth is 12Gbit/s. Output eDP 1.4 1,2 or 4 lanes up to 5.4Gbit/s. output up to 4096x2304 60fps.
上传时间： 2021-12-22
上传用户：
高通(Qualcomm)蓝牙芯片QCC5151_硬件设计详细指导书（官方内部培训手册）共52页其内容是针对硬件设计、部分重要元器件选择(ESD，Filter）及走线注意事项的详细说明。2 Power management 2.1 SMPS 2.1.1 Components specification 2.1.2 Input power supply selection 2.1.3 Minimize SMPS EMI emissions 2.1.4 Internal LDOs and digital core decoupling 2.1.5 Powering external components 2.2 Charger 2.2.1 Charger connections.2.2.2 General charger operation2.2.3 Temperature measurement during charging 2.3 SYS_CTRL 3 Bluetooth radio3.1 RF PSU component choice 3.2 RF band-pass filter3.3 Layout (天线 走线的注意事项)4 Audio4.1 Audio bypass capacitors 4.2 Earphone speaker output4.3 Line/Mic input 4.4 Headphone output optimizition5 LED pads 5.1 LED driver 5.2 Digital/Button input 5.3 Analog input5.4 Disabled 6 Reset pin (Reset#)7 QSPIinterface 8 USB interfaces 8.1 USB device port8.1.1 USB connections8.1.2 Layout notes8.1.3 USB charger detection
上传时间： 2022-01-24
上传用户：XuVshu
ADS8329 Verilog fpga 驱动源码，2.7V 至 5.5V 16 位 1MSPS 串行模数转换器 ADC芯片ADS8329数据采集的verilog代码，已经用在工程中，可以做为你的设计参考。( input clock, input timer_clk_r, input reset, output reg sample_over, output reg ad_convn, input ad_eocn, output reg ad_csn, output reg ad_clk, input ad_dout, output reg ad_din, output reg [15:0] ad_data_lock);reg [15:0] ad_data_old;reg [15:0] ad_data_new; reg [19:0] ad_data_temp; reg [15:0] ad_data;reg [4:0] ad_data_cnt;reg [4:0] ad_spi_cnt; reg [5:0] time_dly_cnt; parameter [3:0] state_mac_IDLE = 0, state_mac_0 = 1, state_mac_1 = 2, state_mac_2 = 3, state_mac_3 = 4, state_mac_4 = 5, state_mac_5 = 6, state_mac_6 = 7, state_mac_7 = 8, state_mac_8 = 9, state_mac_9 = 10, state_mac_10 = 11, state_mac_11 = 12, state_mac_12 = 13, state_mac_13 = 14, state_mac_14 = 15; reg [3:0] state_curr;reg [3:0] state_next;
上传时间： 2022-01-30
上传用户：1208020161
