基于cubeMX的stm32L0系列单片机RTC配置及相关寄存器配置代码，可用于低功耗模式下（stop mode）对单片机进行唤醒，无需外部唤醒源，只需配置RTC的内部唤醒功能即可实现，代码亲测可用。
上传时间： 2021-11-16
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STM32H750VBT6核心板 ALTIUM设计硬件原理图+PCB文件，包括完整的原理图和PCB文件，可以做为你的设计参考，PCB 2层板设计，大小85MM*56MM, 带SD，DCMI,QSPI,外扩flash，以太网，RS485，CAN总线, 主要器件信号列表如下：Library Component Count : 29Name Description----------------------------------------------------------------------------------------------------AMS1117 三端稳压芯片BAT54C 表贴肖特基二极管C 无极性贴片电容CRYSTAL_32K CrystalCap CapacitorFPC0.5-24P 贴片FU 贴片保险丝HR911105Header 2 Header, 2-PinLLAN8720 ETH PHYLED Typical RED, GREEN, YELLOW, AMBER GaAs LEDMAX3485PNP PNP三极管Pin HDR2X20 R 贴片电阻Res ResisterSN65HVD230D STM32H750VBT6 Socket SocketTCAP 钽电容TEST-POINT 测试点TSW 轻触开关USB type C W25Qxx 外置FlashXC6206-3.3 SOT-23,XC6206P332MR,MAX8V,100mAXTAL-4P 4脚无源晶振XTAL_3225 Crystal OscillatormicroSD
上传时间： 2021-11-24
上传用户：aben
USB_MICRO USB_MNI USB扁口座 TF卡槽 SOIC8 LQFP32芯片ALTIUM 库（3D PCB封装库）, 3D封装，已在项目中使用，可以做为你的设计参考。详细列表如下：Component Count : 94Component Name-----------------------------------------------32165032-8MHZAMS1117ANT2AntennaBATbuzzerCapCAP-0805CAP-3216CD32Crystal Oscillator 3225HC-06KEY-2PINLED-0603LQFP-100LQFP32LQFP44LQFP44 10X10_LLQFP44 10X10_MLQFP44 10X10_NLQFP48LQFP48 7X7_LLQFP48 7X7_MLQFP48 7X7_NLQFP64 10x10_LLQFP64 10x10_MLQFP64 10x10_NMagMOTONRF24L01NRF24L01-modeOLED-0.96-PIN7QFN20_4X4QFN24_4X4QFN32_5X5remoteRES-0603RFX2401CRPSG90SH1.0mm-4PINSH1.0MM-5PINSH1.0mm-6PINSMA-ANTSMA/DO-214SOIC-8SOP16SOT-23-3SOT-23-5SOT-89SOT-223SPL06-001STM32F030C8T6STM32F030F4P6STM32F103C8T6straight-1x2pinstraight-1x2pin - duplicatestraight-1x2pin - duplicate1straight-1x3pinstraight-1x3pin - duplicatestraight-1x3pin - duplicate1straight-1x4pinstraight-1x4pin - duplicatestraight-1x5pinstraight-1x8pinstraight-1x8pin - duplicatestraight-2x2pinstraight-2x3pinstraight-2x4pinstraight-2x5pinSW-NO/OFF-PIN3SW-SMD1SW-SMD2SWITCH-DIP-6*6*7SX1308TF-CARDTO-263-5TP4056USBUSB_MICROUSB_MNI_BUSB-MICRO-1winding_1x2pinwinding_1x3pinwinding_1x4pinwinding_1x5pinwinding_1x8pinwinding_2x2pinwinding_2x3pinwinding_2x4pinwinding_2x5pinXTAL-5070/SMDXTAL-QC49/SMD
标签： usb
上传时间： 2021-12-02
上传用户：aben
STM32F407单片机开发板PDF原理图+AD集成封装库+主要器件技术手册资料:AD集成封装库列表：Library Component Count : 54Name Description----------------------------------------------------------------------------------------------------24C256 AMS1117ATK-HC05 ATK-HC05BAT BEEP BUTTONC CAPCH340G USB2UARTDDB9 DHT11 数字温湿度传感器HEAD2HEAD2*22 HR911105 HS0038Header 16 Header, 16-PinHeader 2 Header, 2-PinHeader 2X2 Header, 2-Pin, Dual rowHeader 3X2 Header, 3-Pin, Dual rowHeader 4 Header, 4-PinHeader 9X2 Header, 9-Pin, Dual rowIS62WV51216 JTAG KEY_M L LAN8720 ETH PHYLED2 Typical RED, GREEN, YELLOW, AMBER GaAs LEDLSENS LIGHT SENSL_SOP MAX3232 MAX3485 MIC MOS-P IRLML6401/SI2301MP2359 DC DC Step Down ICMPU6050 9轴运动处理传感器NPN 8050/BCW846/BCW847NRF24L01 PHONE_M PNP 8550/BCW68POW R SMBJ TVSSN65HVD230D STM32F407ZET6 STM32F407ZET6TEST-POINT 测试点TFT_LCD TPAD ALIENTEK TPADUSB5USB_A_90 USB-A-90W25X16
上传时间： 2021-12-15
上传用户：ttalli
NCP1399 是高性能电流模式控制器，半桥谐 变换器。此控制器实现 600 V 门驱动、 简化布 局和减少外部组件计数 。built - in 和 Brown - Out 输入函数简化了执行在所有应用程序的控制器。 在 PFC 前阶段的应用 NCP1399 需要设有专用的 输出驱动 PFC 前级控制器。此功能专用 skip-mode 技术进一步提高轻负载效率的整个应 用程序。 NCP1399 提供全套的保护功能允许安全 运行在任何应用程序中。这包括：过载保护，过 流保护以防止硬开关周期， brown- out 检测，打 开光电耦合器检测， 死区自动调整， 过电压（OVP） 和 (OTP) 过温保护
上传时间： 2021-12-17
上传用户：qingfengchizhu
FPGA读取OV5640摄像头数据并通过VGA或LCD屏显示输出的Verilog逻辑源码Quartus工程文件+文档说明，FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。module top( input clk, input rst_n, output cmos_scl, //cmos i2c clock inout cmos_sda, //cmos i2c data input cmos_vsync, //cmos vsync input cmos_href, //cmos hsync refrence,data valid input cmos_pclk, //cmos pxiel clock output cmos_xclk, //cmos externl clock input [7:0] cmos_db, //cmos data output cmos_rst_n, //cmos reset output cmos_pwdn, //cmos power down output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b, //vga blue output sdram_clk, //sdram clock output sdram_cke, //sdram clock enable output sdram_cs_n, //sdram chip select output sdram_we_n, //sdram write enable output sdram_cas_n, //sdram column address strobe output sdram_ras_n, //sdram row address strobe output[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank address output[12:0] sdram_addr, //sdram address inout[15:0] sdram_dq //sdram data);
上传时间： 2021-12-18
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基于FPGA设计的字符VGA LCD显示实验Verilog逻辑源码Quartus工程文件+文档说明,通过字符转换工具将字符转换为 8 进制 mif 文件存放到单端口的 ROM IP 核中，再从ROM 中把转换后的数据读取出来显示到 VGA 上，FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。module top( input clk, input rst_n, //vga output output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b //vga blue );wire video_clk;wire video_hs;wire video_vs;wire video_de;wire[7:0] video_r;wire[7:0] video_g;wire[7:0] video_b;wire osd_hs;wire osd_vs;wire osd_de;wire[7:0] osd_r;wire[7:0] osd_g;wire[7:0] osd_b;assign vga_out_hs = osd_hs;assign vga_out_vs = osd_vs;assign vga_out_r = osd_r[7:3]; //discard low bit dataassign vga_out_g = osd_g[7:2]; //discard low bit dataassign vga_out_b = osd_b[7:3]; //discard low bit data//generate video pixel clockvideo_pll video_pll_m0( .inclk0 (clk ), .c0 (video_clk ));color_bar color_bar_m0( .clk (video_clk ), .rst (~rst_n ), .hs (video_hs ), .vs (video_vs ), .de (video_de ), .rgb_r (video_r ), .rgb_g (video_g ), .rgb_b (video_b ));osd_display osd_display_m0( .rst_n (rst_n ), .pclk (video_clk ), .i_hs (video_hs ), .i_vs (video_vs ), .i_de (video_de ), .i_data ({video_r,video_g,video_b} ), .o_hs (osd_hs ), .o_vs (osd_vs ), .o_de (osd_de ), .o_data ({osd_r,osd_g,osd_b} ));endmodule
上传时间： 2021-12-18
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基于FPGA设计的vga显示测试实验Verilog逻辑源码Quartus工程文件+文档说明，FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。module top( input clk, input rst_n, //vga output output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b //vga blue );wire video_clk;wire video_hs;wire video_vs;wire video_de;wire[7:0] video_r;wire[7:0] video_g;wire[7:0] video_b;assign vga_out_hs = video_hs;assign vga_out_vs = video_vs;assign vga_out_r = video_r[7:3]; //discard low bit dataassign vga_out_g = video_g[7:2]; //discard low bit dataassign vga_out_b = video_b[7:3]; //discard low bit data//generate video pixel clockvideo_pll video_pll_m0( .inclk0(clk), .c0(video_clk));color_bar color_bar_m0( .clk(video_clk), .rst(~rst_n), .hs(video_hs), .vs(video_vs), .de(video_de), .rgb_r(video_r), .rgb_g(video_g), .rgb_b(video_b));endmodule
标签： fpga vga显示 verilog quartus
上传时间： 2021-12-19
上传用户：kingwide
1. Scope ......................................................................................................................................................................... 12. DDR4 SDRAM Package Pinout and Addressing ....................................................................................................... 22.1 DDR4 SDRAM Row for X4,X8 and X16 ................................................................................................................22.2 DDR4 SDRAM Ball Pitch........................................................................................................................................22.3 DDR4 SDRAM Columns for X4,X8 and X16 ..........................................................................................................22.4 DDR4 SDRAM X4/8 Ballout using MO-207......................................................................................................... 22.5 DDR4 SDRAM X16 Ballout using MO-207.............................................................................................................32.6 Pinout Description ..................................................................................................................................................52.7 DDR4 SDRAM Addressing.....................................................................................................................................73. Functional Description ...............................................................................................................................................83.1 Simplified State Diagram ....................................................................................................................................83.2 Basic Functionality..................................................................................................................................................93.3 RESET and Initialization Procedure .....................................................................................................................103.3.1 Power-up Initialization Sequence .............................................................................................................103.3.2 Reset Initialization with Stable Power ......................................................................................................113.4 Register Definition ................................................................................................................................................123.4.1 Programming the mode registers .............................................................................................................123.5 Mode Register ......................................................................................................................................................134. DDR4 SDRAM Command Description and Operation ............................................................................................. 244.1 Command Truth Table ..........................................................................................................................................244.2 CKE Truth Table ...................................................................................................................................................254.3 Burst Length, Type and Order ..............................................................................................................................264.3.1 BL8 Burst order with CRC Enabled .........................................................................................................264.4 DLL-off Mode & DLL on/off Switching procedure ................................................................................................274.4.1 DLL on/off switching procedure ...............................................................................................................274.4.2 DLL “on” to DLL “off” Procedure ..............................................................................................................274.4.3 DLL “off” to DLL “on” Procedure ..............................................................................................................284.5 DLL-off Mode........................................................................................................................................................294.6 Input Clock Frequency Change ............................................................................................................................304.7 Write Leveling.......................................................................................................................................................314.7.1 DRAM setting for write leveling & DRAM termination function in that mode ............................................324.7.2 Procedure Description .............................................................................................................................334.7.3 Write Leveling Mode Exit .........................................................................................................................34
标签： DDR4
上传时间： 2022-01-09
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STM32L053C8T6数据手册Features • Ultra-low-power platform – 1.65 V to 3.6 V power supply – -40 to 125 °C temperature range – 0.27 µA Standby mode (2 wakeup pins) – 0.4 µA Stop mode (16 wakeup lines) – 0.8 µA Stop mode + RTC + 8 KB RAM retention – 139 µA/MHz Run mode at 32 MHz – 3.5 µs wakeup time (from RAM) – 5 µs wakeup time (from Flash) • Core: ARM® 32-bit Cortex®-M0+ with MPU – From 32 kHz up to 32 MHz max. – 0.95 DMIPS/MHz • Reset and supply management – Ultra-safe, low-power BOR (brownout reset) with 5 selectable thresholds – Ultralow power POR/PDR – Programmable voltage detector (PVD) • Clock sources – 1 to 25 MHz crystal oscillator – 32 kHz oscillator for RTC with calibration – High speed internal 16 MHz factory-trimmed RC (+/- 1%) – Internal low-power 37 kHz RC – Internal multispeed low-power 65 kHz to 4.2 MHz RC – PLL for CPU clock • Pre-programmed bootloader – USART, SPI supported • Development support – Serial wire debug supported • Up to 51 fast I/Os (45 I/Os 5V tolerant) • Memories – Up to 64 KB Flash with ECC – 8KB RAM – 2 KB of data EEPROM with ECC – 20-byte backup register
标签： stm32l053c8t6
上传时间： 2022-02-06
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