代码搜索：wb_master

找到约 17 项符合「wb_master」的源代码

代码结果 17
热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
www.eeworm.com/read/198751/7912834

areasrr rpt_wb_master.areasrr

#### START OF AREA REPORT #####[ Part: XC2S200PQ208-6 (Xilinx) ------------------------------------------------------------------------- ######## Utilization report for Top level view: W
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www.eeworm.com/read/198751/7913259

vtc wb_master.vtc

// // Verplex constraint file // Generated using Synplify-pro // // Copyright (c) 1996-2002 Synplicity, Inc. // All rights reserved // // Set parsing options set log file WB_Master.vlf -repl
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www.eeworm.com/read/354895/10317060

v tb_top.v

////////////////////////////////////////////////////////////////////// //// //// //// Real Time Clock Testbench Top
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www.eeworm.com/read/198751/7912369

plg wb_master.plg

@P: Worst Slack : 988.165 @P: WB_Master|wb_clk_i - Estimated Frequency : 84.5 MHz @P: WB_Master|wb_clk_i - Requested Frequency : 1.0 MHz @P: WB_Master|wb_clk_i - Estimated Period : 11.835 @P:
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www.eeworm.com/read/198751/7912753

tlg wb_master.tlg

Selecting top level module WB_Master Synthesizing module WB_Master @N: CL201 :"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\WB_Master.v":101:0:101:5|Trying to extract state machine for registe
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www.eeworm.com/read/198751/7912584

sdc wb_master_fsm.sdc

log_puts {@N|Using encoding styles selected by FSM Explorer.} log_puts {Data created on Mon Mar 13 22:15:49 2006} define_attribute {work.WB_Master.verilog|i:state[3:0]} syn_encoding {sequential}
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www.eeworm.com/read/487988/1234458

repository

pci/wb_master
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www.eeworm.com/read/198751/7912921

vif wb_master.vif

# # Synplicity Verification Interface File # Generated using Synplify-pro # # Copyright (c) 1996-2004 Synplicity, Inc. # All rights reserved # # Set logfile options vif_set_result_file WB_M
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www.eeworm.com/read/198751/7913107

edn wb_master.edn

(edif (rename wb_master "WB_Master") (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0)) (status (written (timeStamp 2006 3 13 22 17 28) (author "Synplicity,
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www.eeworm.com/read/141580/5769596

lst sim_file_list.lst

../../../../bench/verilog/tb_ethernet.v ../../../../bench/verilog/tb_eth_defines.v ../../../../bench/verilog/eth_phy.v ../../../../bench/verilog/eth_phy_defines.v ../../../../bench/verilog/wb_bus_mon.
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