wb_master.tlg

这是用pci-wishbone核和16450串口核在xilinx的fpga上实现的串口程序

Selecting top level module WB_Master
Synthesizing module WB_Master
@N: CL201 :"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\WB_Master.v":101:0:101:5|Trying to extract state machine for register state
Extracted state machine for register state
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\WB_Master.v":55:13:55:27|Input port bit <1> of dma_base_addr_i[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\WB_Master.v":55:13:55:27|Input port bit <0> of dma_base_addr_i[31:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\WB_Master.v":56:13:56:24|Input port bit <1> of dma_length_i[16:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\WB_Master.v":56:13:56:24|Input port bit <0> of dma_length_i[16:0] is unused

@W: CL159 :"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\WB_Master.v":52:25:52:33|Input wbm_err_i is unused
@W: CL159 :"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\WB_Master.v":52:36:52:44|Input wbm_rty_i is unused