wb_master.plg

来自「这是用pci-wishbone核和16450串口核在xilinx的fpga上实现」· PLG 代码 · 共 17 行

@P:  Worst Slack : 988.165
@P:  WB_Master|wb_clk_i - Estimated Frequency : 84.5 MHz
@P:  WB_Master|wb_clk_i - Requested Frequency : 1.0 MHz
@P:  WB_Master|wb_clk_i - Estimated Period : 11.835
@P:  WB_Master|wb_clk_i - Requested Period : 1000.000
@P:  WB_Master|wb_clk_i - Slack : 988.165
@P:  System - Estimated Frequency : 93.7 MHz
@P:  System - Requested Frequency : 1.0 MHz
@P:  System - Estimated Period : 10.668
@P:  System - Requested Period : 1000.000
@P:  System - Slack : 989.332
@P: WB_Master Part : xc2s200pq208-6
@P: WB_Master I/O primitives : 211
@P: WB_Master I/O Register bits : 0
@P: WB_Master Register bits (Non I/O) : 143 (3%)
@P: WB_Master Total Luts : 88 (1%)