wb_master_fsm.sdc

来自「这是用pci-wishbone核和16450串口核在xilinx的fpga上实现」· SDC 代码 · 共 6 行

log_puts {@N|Using encoding styles selected by FSM Explorer.}
log_puts {Data created on Mon Mar 13 22:15:49 2006}

define_attribute {work.WB_Master.verilog|i:state[3:0]} syn_encoding {sequential}