wb_master.vtc

这是用pci-wishbone核和16450串口核在xilinx的fpga上实现的串口程序

//
// Verplex constraint file
// Generated using Synplify-pro
//
// Copyright (c) 1996-2002 Synplicity, Inc.
// All rights reserved
//

// Set parsing options
set log file WB_Master.vlf -replace
set naming rule "%s_Z" -register -golden
set naming rule "%s" -register -revised
set case sensitivity off
// set undriven signal 0 -both
// set undefined cell black_box -noascend

// Read golden and revised designs
read design -file lec/WB_Master.vlc -verilog \
 	D:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v \
 	./WB_Master.v \
	-golden -root WB_Master
read design -file lec/WB_Master.vlc -verilog WB_Master.vm -revised -root WB_Master

// Generate parsing report
report messages
report black box
report design data
report floating signals

// Read FSM encoding
read fsm encoding lec/state_0.vfc

// Read setup constraints
read setup file lec/WB_Master.vsc

// Set mapping options
add renaming rule rulerr "\/Q_r_e_g" "" -revised
add renaming rule rulegh "_Z\[%d\]\[%d\]" "_@1__Z[@2]" -golden
add renaming rule rulegt "_Z\[%d\]$" "[@1]" -type DFF -type DLAT -golden
add renaming rule rulert "_Z\[%d\]$" "[@1]" -type DFF -type DLAT -revised
add renaming rule rulego "_Z$" "" -type DFF -type DLAT -golden
add renaming rule rulero "_Z$" "" -type DFF -type DLAT -revised
set flatten model -seq_constant
// set flatten model -mux_loop_to_dlat
// set flatten model -all_seq_merge
// set flatten model -self_seq_merge
set mapping method -name first

// Run equivalence checker
set sys mode lec -nomap
read map point lec/WB_Master.vmc
map key point
add compare point -all
compare
usage
// exit -f