wb_master.vif

这是用pci-wishbone核和16450串口核在xilinx的fpga上实现的串口程序

#
# Synplicity Verification Interface File
# Generated using Synplify-pro
#
# Copyright (c) 1996-2004 Synplicity, Inc.
# All rights reserved
#

# Set logfile options
vif_set_result_file  WB_Master.vlf

# RTL and technology files
vif_add_library -original $XILINX/verilog/verification/unisims
vif_add_library -original $XILINX/verilog/verification/simprims
vif_add_file -original  -verilog D:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v
vif_add_file -original  -verilog ./WB_Master.v
vif_set_top_module -original -top WB_Master
 
vif_add_library -translated $XILINX/verilog/verification/unisims
vif_add_library -translated $XILINX/verilog/verification/simprims
vif_add_file -translated -verilog WB_Master.vm
vif_set_top_module -translated -top WB_Master 


# Read FSM encoding
vif_set_fsm -fsm fsm_0
vif_set_fsmreg -original -fsm fsm_0 state_Z[1:0]
vif_set_fsmreg -translated -fsm  fsm_0 state_Z[1:0]
vif_set_state_map -fsm fsm_0 -original "00" -translated "00"
vif_set_state_map -fsm fsm_0 -original "01" -translated "01"
vif_set_state_map -fsm fsm_0 -original "10" -translated "10"
vif_set_state_map -fsm fsm_0 -original "11" -translated "11"


# Memory map points
# Memory redundancies


# SRL redundancies
# SRL map points


# RTL sequential redundancies

# Technology sequential redundancies
vif_set_equiv -inverted -translated wbm_we_o_Z wbm_we_o_rep0_i_Z

# Inverted map points

# Port directions

# Black box mapping


# Register pruning