wb_master.edn

这是用pci-wishbone核和16450串口核在xilinx的fpga上实现的串口程序

(edif (rename wb_master "WB_Master")
  (edifVersion 2 0 0)
  (edifLevel 0)
  (keywordMap (keywordLevel 0))
  (status
    (written
      (timeStamp 2006 3 13 22 17 28)
      (author "Synplicity, Inc.")
      (program "Synplify Pro" (version "7.6.0, Build 080R"))
     )
   )
  (library VIRTEX
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell IBUFG (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port O (direction OUTPUT))
           (port I (direction INPUT))
         )
       )
    )
    (cell IBUF (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port O (direction OUTPUT))
           (port I (direction INPUT))
         )
       )
    )
    (cell OBUF (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port O (direction OUTPUT))
           (port I (direction INPUT))
         )
       )
    )
    (cell LUT4 (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I0 (direction INPUT))
           (port I1 (direction INPUT))
           (port I2 (direction INPUT))
           (port I3 (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell LUT3 (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I0 (direction INPUT))
           (port I1 (direction INPUT))
           (port I2 (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell LUT2 (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I0 (direction INPUT))
           (port I1 (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell LUT1 (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I0 (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell XORCY (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port LI (direction INPUT))
           (port CI (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell MUXCY_L (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port DI (direction INPUT))
           (port CI (direction INPUT))
           (port S (direction INPUT))
           (port LO (direction OUTPUT))
         )
       )
    )
    (cell MUXCY (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port DI (direction INPUT))
           (port CI (direction INPUT))
           (port S (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell BUFG (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
  )
  (library UNILIB
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell FDC (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port Q (direction OUTPUT))
           (port D (direction INPUT))
           (port C (direction INPUT)
 )
           (port CLR (direction INPUT))
         )
       )
    )
    (cell FDPE (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port Q (direction OUTPUT))
           (port D (direction INPUT))
           (port C (direction INPUT)
 )
           (port PRE (direction INPUT))
           (port CE (direction INPUT))
         )
       )
    )
    (cell FDCE (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port Q (direction OUTPUT))
           (port D (direction INPUT))
           (port C (direction INPUT)
 )
           (port CLR (direction INPUT))
           (port CE (direction INPUT))
         )
       )
    )
    (cell INV (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell GND (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port G (direction OUTPUT))
         )
       )
    )
    (cell VCC (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port P (direction OUTPUT))
         )
       )
    )
  )
  (library work
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell (rename wb_master "WB_Master") (cellType GENERIC)
       (view verilog (viewType NETLIST)
         (interface
           (port (array (rename wbm_sel_o "wbm_sel_o[3:0]") 4) (direction OUTPUT))
           (port (array (rename wbm_adr_o "wbm_adr_o[31:0]") 32) (direction OUTPUT))
           (port (array (rename wbm_dat_o "wbm_dat_o[31:0]") 32) (direction OUTPUT))
           (port (array (rename wbm_cti_o "wbm_cti_o[2:0]") 3) (direction OUTPUT))
           (port (array (rename wbm_bte_o "wbm_bte_o[1:0]") 2) (direction OUTPUT))
           (port (array (rename wbm_dat_i "wbm_dat_i[31:0]") 32) (direction INPUT))
           (port (array (rename dma_base_addr_i "dma_base_addr_i[31:0]") 32) (direction INPUT))
           (port (array (rename dma_length_i "dma_length_i[16:0]") 17) (direction INPUT))
           (port (array (rename sram_addr_o "sram_addr_o[15:0]") 16) (direction OUTPUT))
           (port (array (rename sram_data_i "sram_data_i[15:0]") 16) (direction INPUT))
           (port (array (rename sram_data_o "sram_data_o[15:0]") 16) (direction OUTPUT))
           (port wb_clk_i (direction INPUT)
 )
           (port wb_rst_i (direction INPUT)
 )
           (port wb_int_o (direction OUTPUT))
           (port wbm_cyc_o (direction OUTPUT))
           (port wbm_stb_o (direction OUTPUT))
           (port wbm_we_o (direction OUTPUT))
           (port wbm_cab_o (direction OUTPUT))
           (port wbm_ack_i (direction INPUT)
 )
           (port wbm_err_i (direction INPUT)
 )
           (port wbm_rty_i (direction INPUT)
 )
           (port dma_rw_i (direction INPUT)
 )
           (port dma_start_i (direction INPUT)
 )
           (port sram_oe_o (direction OUTPUT))
           (port sram_we_o (direction OUTPUT))
           (port sram_ce_o (direction OUTPUT))
         )
         (contents
          (instance state31_axb_0_i (viewRef PRIM (cellRef LUT2 (libraryRef VIRTEX)))
           (property init (string "9"))
          )
          (instance state31_axb_1_i (viewRef PRIM (cellRef LUT2 (libraryRef VIRTEX)))
           (property init (string "9"))
          )
          (instance state31_axb_2_i (viewRef PRIM (cellRef LUT2 (libraryRef VIRTEX)))
           (property init (string "9"))
          )
          (instance state31_axb_3_i (viewRef PRIM (cellRef LUT2 (libraryRef VIRTEX)))
           (property init (string "9"))
          )
          (instance state31_axb_4_i (viewRef PRIM (cellRef LUT2 (libraryRef VIRTEX)))
           (property init (string "9"))
          )
          (instance state31_axb_5_i (viewRef PRIM (cellRef LUT2 (libraryRef VIRTEX)))
           (property init (string "9"))
          )