代码搜索：vhdl

找到约 10,000 项符合「vhdl」的源代码

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热门代码： main.c GPIO I2C SPI UART timer interrupt ADC PWM LED
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hif fenpin.hif

Version 4.1 Build 181 06/29/2004 SJ Full Version 28 OFF OFF OFF OFF 0 # entity fenpin # logic_option { AUTO_RAM_RECOGNITION ON } # case_insensitive # source_file fenpin.vhd 1241941426
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www.eeworm.com/read/412366/11202512

hif dispselector.hif

Version 4.1 Build 181 06/29/2004 SJ Full Version 28 OFF OFF OFF OFF 0 # entity dispselector # logic_option { AUTO_RAM_RECOGNITION ON } # case_insensitive # source_file dispselector.vhd
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www.eeworm.com/read/412366/11203065

hif selector.hif

Version 4.1 Build 181 06/29/2004 SJ Full Version 28 OFF OFF OFF OFF 0 # entity selector # logic_option { AUTO_RAM_RECOGNITION ON } # case_insensitive # source_file selector.vhd 1196666
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www.eeworm.com/read/412366/11203429

hif counter.hif

Version 4.1 Build 181 06/29/2004 SJ Full Version 28 OFF OFF OFF OFF 0 # entity counter # logic_option { AUTO_RAM_RECOGNITION ON } # case_insensitive # source_file counter.vhd 119917699
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www.eeworm.com/read/433021/8552168

tbw count_sim.tbw

version 3 counter.vhd counter VHDL VHDL count_sim.xwv Clocked - - 330000000 ns GSR:false PRLD:false 100000000 CLOCK_LIST_BEGIN CLK 50000000 50000000 10000000 10000000 0 RISING CL
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www.eeworm.com/read/169299/9868360

vhd mdecode_timesim.vhd

-- Xilinx Vhdl netlist produced by netgen application (version G.35) -- Command : -rpw 100 -ar Structure -xon true -w -ofmt vhdl -sim mdecode.nga mdecode_timesim.vhd -- Input file : mdecode.
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www.eeworm.com/read/351812/10608102

ini modelsim.ini

[Library] others = $MODEL_TECH/../modelsim.ini ; Altera specific primitive library mappings work = rtl_work [vcom] ; Turn on VHDL-1993 as the default. Normally is off. ; VHDL93 = 1 ; Sho
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www.eeworm.com/read/349103/10851621

vhd drink-cnt.vhd

entity DRINK_COUNT_VHDL is port(NICKEL_IN, DIME_IN, QUARTER_IN, RESET: BOOLEAN; CLK: BIT; NICKEL_OUT, DIME_OUT, DISPENSE: out BOOLEAN); end; architecture BEHAVIOR of DRINK_COUNT_VHDL
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www.eeworm.com/read/493986/6386071

tbw testmachine2.tbw

version 3 fsm.vhd fsm VHDL VHDL testMachine2.xwv Clocked - - 1000000000 ns GSR:false PRLD:false 100000000 CLOCK_LIST_BEGIN SCLK 50000000 50000000 10000000 10000000 0 RISING CLOCK
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www.eeworm.com/read/210233/15203379

vhw qd_tw.vhw

-- E:\VHDL\WAITPAST\QIANGDAQI4REN -- VHDL Test Bench created by -- HDL Bencher 6.1i -- Sat Mar 24 14:51:18 2007 -- -- Notes: -- 1) This testbench has been automatically generated from -- you
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