mdecode_timesim.vhd

xilinx xc9572 cpld 实现的伺服电机控制器

-- Xilinx Vhdl netlist produced by netgen application (version G.35)
-- Command       : -rpw 100 -ar Structure -xon true -w -ofmt vhdl -sim mdecode.nga mdecode_timesim.vhd 
-- Input file    : mdecode.nga
-- Output file   : mdecode_timesim.vhd
-- Design name   : mdecode.nga
-- # of Entities : 1
-- Xilinx        : D:/Xilinx
-- Device        : XC9572-10-TQ100 (Speed File: Version 3.0)

-- This vhdl netlist is a simulation model and uses simulation 
-- primitives which may not represent the true implementation of the 
-- device, however the netlist is functionally correct and should not 
-- be modified. This file cannot be synthesized and should only be used 
-- with supported simulation tools.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity mdecode is
  port (
    CLR1 : in STD_LOGIC := 'X'; 
    MA1 : in STD_LOGIC := 'X'; 
    MB1 : in STD_LOGIC := 'X'; 
    CLR0 : in STD_LOGIC := 'X'; 
    MA0 : in STD_LOGIC := 'X'; 
    MB0 : in STD_LOGIC := 'X'; 
    MC0 : in STD_LOGIC := 'X'; 
    MC1 : in STD_LOGIC := 'X'; 
    RD : in STD_LOGIC := 'X'; 
    O : out STD_LOGIC_VECTOR ( 7 downto 0 ) 
  );
end mdecode;

architecture Structure of mdecode is
  signal CLR1_IBUF : STD_LOGIC; 
  signal MA1_IBUF : STD_LOGIC; 
  signal MB1_IBUF : STD_LOGIC; 
  signal CLR0_IBUF : STD_LOGIC; 
  signal MA0_IBUF : STD_LOGIC; 
  signal MB0_IBUF : STD_LOGIC; 
  signal MC0_IBUF : STD_LOGIC; 
  signal MC1_IBUF : STD_LOGIC; 
  signal RD_IBUF : STD_LOGIC; 
  signal O_0 : STD_LOGIC; 
  signal O_1 : STD_LOGIC; 
  signal O_2 : STD_LOGIC; 
  signal O_3 : STD_LOGIC; 
  signal O_4 : STD_LOGIC; 
  signal O_5 : STD_LOGIC; 
  signal O_6 : STD_LOGIC; 
  signal O_7 : STD_LOGIC; 
  signal Q41_0_Q : STD_LOGIC; 
  signal Q41_0_Q_0 : STD_LOGIC; 
  signal Q41_0_FBK : STD_LOGIC; 
  signal Q41_0_D : STD_LOGIC; 
  signal Q41_0_tsimcreated_xor_Q : STD_LOGIC; 
  signal Q41_0_RSTF : STD_LOGIC; 
  signal PRLD : STD_LOGIC; 
  signal Q41_0_tsimcreated_prld_Q : STD_LOGIC; 
  signal Q41_0_CLKF : STD_LOGIC; 
  signal Gnd : STD_LOGIC; 
  signal Vcc : STD_LOGIC; 
  signal Q41_0_D1 : STD_LOGIC; 
  signal Q41_0_D2 : STD_LOGIC; 
  signal Q41_0_D2_PT_0 : STD_LOGIC; 
  signal Q41_0_D2_PT_1 : STD_LOGIC; 
  signal Q41_2_Q41_2_CLKF_INT_FBK : STD_LOGIC; 
  signal Q4_0_Q : STD_LOGIC; 
  signal Q4_0_FBK : STD_LOGIC; 
  signal Q4_0_D : STD_LOGIC; 
  signal Q4_0_tsimcreated_xor_Q : STD_LOGIC; 
  signal Q4_0_RSTF : STD_LOGIC; 
  signal Q4_0_tsimcreated_prld_Q : STD_LOGIC; 
  signal Q4_0_CLKF : STD_LOGIC; 
  signal Q4_0_D1 : STD_LOGIC; 
  signal Q4_0_D2 : STD_LOGIC; 
  signal Q4_0_D2_PT_0 : STD_LOGIC; 
  signal Q4_0_D2_PT_1 : STD_LOGIC; 
  signal Q4_2_Q4_2_CLKF_INT_FBK : STD_LOGIC; 
  signal Q41_1_Q : STD_LOGIC; 
  signal Q41_1_FBK : STD_LOGIC; 
  signal Q41_1_D : STD_LOGIC; 
  signal Q41_1_tsimcreated_xor_Q : STD_LOGIC; 
  signal Q41_1_RSTF : STD_LOGIC; 
  signal Q41_1_tsimcreated_prld_Q : STD_LOGIC; 
  signal Q41_1_CLKF : STD_LOGIC; 
  signal Q41_1_D1 : STD_LOGIC; 
  signal Q41_1_D2 : STD_LOGIC; 
  signal Q41_1_D2_PT_0 : STD_LOGIC; 
  signal Q41_1_D2_PT_1 : STD_LOGIC; 
  signal Q4_1_Q : STD_LOGIC; 
  signal Q4_1_FBK : STD_LOGIC; 
  signal Q4_1_D : STD_LOGIC; 
  signal Q4_1_tsimcreated_xor_Q : STD_LOGIC; 
  signal Q4_1_RSTF : STD_LOGIC; 
  signal Q4_1_tsimcreated_prld_Q : STD_LOGIC; 
  signal Q4_1_CLKF : STD_LOGIC; 
  signal Q4_1_D1 : STD_LOGIC; 
  signal Q4_1_D2 : STD_LOGIC; 
  signal Q4_1_D2_PT_0 : STD_LOGIC; 
  signal Q4_1_D2_PT_1 : STD_LOGIC; 
  signal Q41_2_Q : STD_LOGIC; 
  signal Q41_2_Q_1 : STD_LOGIC; 
  signal Q41_2_D : STD_LOGIC; 
  signal Q41_2_tsimcreated_xor_Q : STD_LOGIC; 
  signal Q41_2_RSTF : STD_LOGIC; 
  signal Q41_2_tsimcreated_prld_Q : STD_LOGIC; 
  signal Q41_2_CLKF : STD_LOGIC; 
  signal Q41_2_D1 : STD_LOGIC; 
  signal Q41_2_D2 : STD_LOGIC; 
  signal Q41_2_D2_PT_0 : STD_LOGIC; 
  signal Q41_2_D2_PT_1 : STD_LOGIC; 
  signal Q4_2_Q : STD_LOGIC; 
  signal Q4_2_D : STD_LOGIC; 
  signal Q4_2_tsimcreated_xor_Q : STD_LOGIC; 
  signal Q4_2_RSTF : STD_LOGIC; 
  signal Q4_2_tsimcreated_prld_Q : STD_LOGIC; 
  signal Q4_2_CLKF : STD_LOGIC; 
  signal Q4_2_D1 : STD_LOGIC; 
  signal Q4_2_D2 : STD_LOGIC; 
  signal Q4_2_D2_PT_0 : STD_LOGIC; 
  signal Q4_2_D2_PT_1 : STD_LOGIC; 
  signal Q41_3_Q : STD_LOGIC; 
  signal Q41_3_FBK : STD_LOGIC; 
  signal Q41_3_D : STD_LOGIC; 
  signal Q41_3_tsimcreated_xor_Q : STD_LOGIC; 
  signal Q41_3_RSTF : STD_LOGIC; 
  signal Q41_3_tsimcreated_prld_Q : STD_LOGIC; 
  signal Q41_3_CLKF : STD_LOGIC; 
  signal Q41_3_D1 : STD_LOGIC; 
  signal Q41_3_D2 : STD_LOGIC; 
  signal Q41_3_D2_PT_0 : STD_LOGIC; 
  signal Q41_3_D2_PT_1 : STD_LOGIC; 
  signal Q4_3_Q : STD_LOGIC; 
  signal Q4_3_FBK : STD_LOGIC; 
  signal Q4_3_D : STD_LOGIC; 
  signal Q4_3_tsimcreated_xor_Q : STD_LOGIC; 
  signal Q4_3_RSTF : STD_LOGIC; 
  signal Q4_3_tsimcreated_prld_Q : STD_LOGIC; 
  signal Q4_3_CLKF : STD_LOGIC; 
  signal Q4_3_D1 : STD_LOGIC; 
  signal Q4_3_D2 : STD_LOGIC; 
  signal Q4_3_D2_PT_0 : STD_LOGIC; 
  signal Q4_3_D2_PT_1 : STD_LOGIC; 
  signal O_0_Q : STD_LOGIC; 
  signal O_0_RSTF : STD_LOGIC; 
  signal O_0_SETF : STD_LOGIC; 
  signal O_0_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal O_0_tsimcreated_prld_Q : STD_LOGIC; 
  signal O_0_D : STD_LOGIC; 
  signal O_0_CLKF : STD_LOGIC; 
  signal O_0_D1 : STD_LOGIC; 
  signal O_0_D2 : STD_LOGIC; 
  signal O_1_Q : STD_LOGIC; 
  signal O_1_RSTF : STD_LOGIC; 
  signal O_1_SETF : STD_LOGIC; 
  signal O_1_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal O_1_tsimcreated_prld_Q : STD_LOGIC; 
  signal O_1_D : STD_LOGIC; 
  signal O_1_CLKF : STD_LOGIC; 
  signal O_1_D1 : STD_LOGIC; 
  signal O_1_D2 : STD_LOGIC; 
  signal O_2_Q : STD_LOGIC; 
  signal O_2_RSTF : STD_LOGIC; 
  signal O_2_SETF : STD_LOGIC; 
  signal O_2_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal O_2_tsimcreated_prld_Q : STD_LOGIC; 
  signal O_2_D : STD_LOGIC; 
  signal O_2_CLKF : STD_LOGIC; 
  signal O_2_D1 : STD_LOGIC; 
  signal O_2_D2 : STD_LOGIC; 
  signal O_3_Q : STD_LOGIC; 
  signal O_3_RSTF : STD_LOGIC; 
  signal O_3_SETF : STD_LOGIC; 
  signal O_3_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal O_3_tsimcreated_prld_Q : STD_LOGIC; 
  signal O_3_D : STD_LOGIC; 
  signal O_3_CLKF : STD_LOGIC; 
  signal O_3_D1 : STD_LOGIC; 
  signal O_3_D2 : STD_LOGIC; 
  signal O_4_Q : STD_LOGIC; 
  signal O_4_RSTF : STD_LOGIC; 
  signal O_4_SETF : STD_LOGIC; 
  signal O_4_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal O_4_tsimcreated_prld_Q : STD_LOGIC; 
  signal O_4_D : STD_LOGIC; 
  signal O_4_CLKF : STD_LOGIC; 
  signal O_4_D1 : STD_LOGIC; 
  signal O_4_D2 : STD_LOGIC; 
  signal O_5_Q : STD_LOGIC; 
  signal O_5_RSTF : STD_LOGIC; 
  signal O_5_SETF : STD_LOGIC; 
  signal O_5_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal O_5_tsimcreated_prld_Q : STD_LOGIC; 
  signal O_5_D : STD_LOGIC; 
  signal O_5_CLKF : STD_LOGIC; 
  signal O_5_D1 : STD_LOGIC; 
  signal O_5_D2 : STD_LOGIC; 
  signal O_6_Q : STD_LOGIC; 
  signal O_6_RSTF : STD_LOGIC; 
  signal O_6_SETF : STD_LOGIC; 
  signal O_6_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal O_6_tsimcreated_prld_Q : STD_LOGIC; 
  signal O_6_D : STD_LOGIC; 
  signal O_6_CLKF : STD_LOGIC; 
  signal O_6_D1 : STD_LOGIC; 
  signal O_6_D2 : STD_LOGIC; 
  signal O_7_Q : STD_LOGIC; 
  signal O_7_RSTF : STD_LOGIC; 
  signal O_7_SETF : STD_LOGIC; 
  signal O_7_tsimcreated_set_and_noreset_Q : STD_LOGIC; 
  signal O_7_tsimcreated_prld_Q : STD_LOGIC; 
  signal O_7_D : STD_LOGIC; 
  signal O_7_CLKF : STD_LOGIC; 
  signal O_7_D1 : STD_LOGIC; 
  signal O_7_D2 : STD_LOGIC; 
  signal Q41_2_Q41_2_CLKF_INT_Q : STD_LOGIC; 
  signal Q41_2_Q41_2_CLKF_INT_D : STD_LOGIC; 
  signal Q41_2_Q41_2_CLKF_INT_D1 : STD_LOGIC; 
  signal Q41_2_Q41_2_CLKF_INT_D2 : STD_LOGIC; 
  signal Q4_2_Q4_2_CLKF_INT_Q : STD_LOGIC; 
  signal Q4_2_Q4_2_CLKF_INT_D : STD_LOGIC; 
  signal Q4_2_Q4_2_CLKF_INT_D1 : STD_LOGIC; 
  signal Q4_2_Q4_2_CLKF_INT_D2 : STD_LOGIC; 
  signal NlwInverterSignal_Q41_0_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Q41_0_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Q41_0_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Q41_0_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Q4_0_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Q4_0_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Q4_0_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Q4_0_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Q41_1_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Q41_1_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Q41_1_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Q41_1_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Q41_1_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Q4_1_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Q4_1_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Q4_1_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Q4_1_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Q4_1_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Q41_2_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Q41_2_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Q41_2_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Q41_2_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_Q41_2_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Q41_2_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Q4_2_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Q4_2_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Q4_2_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Q4_2_D2_PT_1_IN3 : STD_LOGIC; 
  signal NlwInverterSignal_Q4_2_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Q4_2_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Q41_3_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Q41_3_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Q41_3_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Q41_3_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Q41_3_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Q4_3_D2_PT_0_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Q4_3_D2_PT_1_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Q4_3_D2_PT_1_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Q4_3_CLKF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_Q4_3_CLKF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_O_0_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_O_0_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_O_0_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_O_0_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_O_1_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_O_1_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_O_1_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_O_1_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_O_2_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_O_2_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_O_2_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_O_2_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_O_3_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_O_3_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_O_3_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_O_3_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_O_4_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_O_4_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_O_4_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_O_4_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_O_5_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_O_5_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_O_5_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_O_5_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_O_6_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_O_6_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_O_6_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_O_6_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_O_7_tsimcreated_set_and_noreset_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_O_7_SETF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_O_7_RSTF_IN0 : STD_LOGIC; 
  signal NlwInverterSignal_O_7_RSTF_IN1 : STD_LOGIC; 
  signal NlwInverterSignal_Q41_2_Q41_2_CLKF_INT_D2_IN2 : STD_LOGIC; 
  signal NlwInverterSignal_Q4_2_Q4_2_CLKF_INT_D2_IN2 : STD_LOGIC; 
  signal Q4 : STD_LOGIC_VECTOR ( 3 downto 0 ); 
begin
  CLR1_IBUF_2 : X_BUF
    port map (
      I => CLR1,
      O => CLR1_IBUF
    );
  MA1_IBUF_3 : X_BUF
    port map (
      I => MA1,
      O => MA1_IBUF
    );
  MB1_IBUF_4 : X_BUF
    port map (
      I => MB1,
      O => MB1_IBUF
    );
  CLR0_IBUF_5 : X_BUF
    port map (
      I => CLR0,
      O => CLR0_IBUF
    );
  MA0_IBUF_6 : X_BUF
    port map (
      I => MA0,
      O => MA0_IBUF
    );
  MB0_IBUF_7 : X_BUF
    port map (
      I => MB0,
      O => MB0_IBUF
    );
  MC0_IBUF_8 : X_BUF
    port map (
      I => MC0,
      O => MC0_IBUF
    );
  MC1_IBUF_9 : X_BUF
    port map (
      I => MC1,
      O => MC1_IBUF
    );
  RD_IBUF_10 : X_BUF
    port map (
      I => RD,
      O => RD_IBUF
    );
  O_0_Q_11 : X_BUF
    port map (
      I => O_0,
      O => O(0)
    );
  O_1_Q_12 : X_BUF
    port map (
      I => O_1,
      O => O(1)
    );
  O_2_Q_13 : X_BUF
    port map (
      I => O_2,
      O => O(2)
    );
  O_3_Q_14 : X_BUF
    port map (
      I => O_3,
      O => O(3)
    );
  O_4_Q_15 : X_BUF
    port map (
      I => O_4,
      O => O(4)
    );
  O_5_Q_16 : X_BUF
    port map (
      I => O_5,
      O => O(5)
    );
  O_6_Q_17 : X_BUF
    port map (
      I => O_6,
      O => O(6)
    );
  O_7_Q_18 : X_BUF
    port map (
      I => O_7,
      O => O(7)
    );
  Q41_0_Q_19 : X_BUF
    port map (
      I => Q41_0_Q,
      O => Q41_0_Q_0
    );
  Q41_0_FBK_20 : X_BUF
    port map (
      I => Q41_0_Q,
      O => Q41_0_FBK
    );
  Q41_0_tsimcreated_xor_Q_21 : X_XOR2
    port map (
      I0 => Q41_0_D,
      I1 => Q41_0_Q,
      O => Q41_0_tsimcreated_xor_Q
    );
  Q41_0_tsimcreated_prld_Q_22 : X_OR2
    port map (
      I0 => Q41_0_RSTF,
      I1 => PRLD,
      O => Q41_0_tsimcreated_prld_Q
    );
  Q41_0_REG : X_FF
    port map (
      I => Q41_0_tsimcreated_xor_Q,
      CE => Vcc,
      CLK => Q41_0_CLKF,
      SET => Gnd,
      RST => Q41_0_tsimcreated_prld_Q,
      O => Q41_0_Q
    );
  Gnd_23 : X_ZERO
    port map (
      O => Gnd
    );
  Vcc_24 : X_ONE
    port map (
      O => Vcc
    );
  Q41_0_D_25 : X_XOR2
    port map (
      I0 => Q41_0_D1,
      I1 => Q41_0_D2,
      O => Q41_0_D
    );
  Q41_0_D1_26 : X_ZERO
    port map (
      O => Q41_0_D1
    );
  Q41_0_D2_PT_0_27 : X_AND2
    port map (
      I0 => MA1_IBUF,
      I1 => NlwInverterSignal_Q41_0_D2_PT_0_IN1,
      O => Q41_0_D2_PT_0
    );
  Q41_0_D2_PT_1_28 : X_AND2
    port map (
      I0 => NlwInverterSignal_Q41_0_D2_PT_1_IN0,
      I1 => MB1_IBUF,
      O => Q41_0_D2_PT_1
    );
  Q41_0_D2_29 : X_OR2
    port map (
      I0 => Q41_0_D2_PT_0,
      I1 => Q41_0_D2_PT_1,
      O => Q41_0_D2
    );
  Q41_0_CLKF_30 : X_AND2
    port map (
      I0 => NlwInverterSignal_Q41_0_CLKF_IN0,
      I1 => NlwInverterSignal_Q41_0_CLKF_IN1,
      O => Q41_0_CLKF