count_sim.tbw

含有各类寄存器

version 3
counter.vhd
counter
VHDL
VHDL
count_sim.xwv
Clocked
-
-
330000000
ns
GSR:false
PRLD:false
100000000
CLOCK_LIST_BEGIN
CLK
50000000
50000000
10000000
10000000
0
RISING
CLOCK_LIST_END
SIGNAL_LIST_BEGIN
RESET
CLK
CE
CLK
LOAD
CLK
DIR
CLK
DIN
CLK
COUNT
CLK
SIGNAL_LIST_END
SIGNALS_NOT_ON_DISPLAY
SIGNALS_NOT_ON_DISPLAY_END
MARKER_LIST_BEGIN
MARKER_LIST_END
MEASURE_LIST_BEGIN
MEASURE_LIST_END
SIGNAL_ORDER_BEGIN
SIGNAL_ORDER_END
-X-X-X-
NOTE: This file was converted from the Granite version