代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/320564/13423293
vhd baheyouxiji.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity baheyouxiji is
port(bego,clk1,cp,left,right,clearhexin,clearxianshi:in std_logic;
www.eeworm.com/read/320564/13423301
vhd hexin.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity hexin is
port(bego,over,left,right,cp,clear:in std_logic;
www.eeworm.com/read/320564/13423313
vhd bahe.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bahe is
port(bego,left,right,cp,clear:in std_logic;--CP 接q18脚
q:inout std_logic_ve
www.eeworm.com/read/320564/13423354
vhd yima.vhd
library ieee;
use ieee.std_logic_1164.all;
entity yima is
port(a,b,c,d:in std_logic;
y: inout std_logic_vector(14 downto 0));
end yima;
architecture one of yima is
signal indat
www.eeworm.com/read/320564/13423357
vhd duolufuyong.vhd
library ieee;
use ieee.std_logic_1164.all;
entity duolufuyong is
port(sa,sb:in std_logic;
a,b:in std_logic_vector(3 downto 0);
q:out std_logic_vector(3 downto 0));
end duolufuy
www.eeworm.com/read/320564/13423621
vhd qiduanyima.vhd
library ieee;
use ieee.std_logic_1164.all;
entity qiduanyima is
port(a,b,c,d:in std_logic;
y:out std_logic_vector(6 downto 0));
end qiduanyima;
architecture one of qiduanyima is
www.eeworm.com/read/320545/13424410
vhd tennis.vhd
library ieee;
use ieee.std_logic_1164.all;
entity TENNIS is
port(bain,bbin,clr,clk,souclk:in std_logic;
ballout:out std_logic_vector(7 downto 0);
countah,countal,countbh,countbl:out std_logic_v
www.eeworm.com/read/319928/13439366
vhd alu.vhd
--实验6.10——实验CPU：算数逻辑单元
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ALU is
port(
reset,clk : in std_logic;
OP:
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vhd tx_encoder.vhd
----------------------------------------------------------------------
---- ----
---- WISHBONE SPDIF IP Core
www.eeworm.com/read/318575/13475618
vhd dport16.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity dport16 is
port(
cin1 : in std_logic;
cin2 : in std_logic;
cout :