📄 qiduanyima.vhd
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library ieee;
use ieee.std_logic_1164.all;
entity qiduanyima is
port(a,b,c,d:in std_logic;
y:out std_logic_vector(6 downto 0));
end qiduanyima;
architecture one of qiduanyima is
signal data:std_logic_vector(3 downto 0);
begin
data<=d&c&b&a;
process(data)
begin
case data is
when"0000"=>y<="0111111";
when"0001"=>y<="0000110";
when"0010"=>y<="1011011";
when"0011"=>y<="1001111";
when"0100"=>y<="1100110";
when"0101"=>y<="1101101";
when"0110"=>y<="1111101";
when"0111"=>y<="0100111";
when"1000"=>y<="1111111";
when"1001"=>y<="1101111";
when others=>y<="1111111";
end case;
end process;
end one;
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