alu.vhd

ALU可以实现16种操作（包括加减乘除移位运算等）

--实验6.10——实验CPU：算数逻辑单元
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity ALU is
	port(
		 reset,clk :	in std_logic;	
		 OP:		    in std_logic_vector(3 downto 0);
		 sel:	        in std_logic;
		 write:			in std_logic;
		 Dinput:        in std_logic_vector(15 downto 0);
		 cin:			in std_logic;
		 result:        out std_logic_vector(15 downto 0);
		 C,Z:			out std_logic
		);
end ALU;

architecture behav of alu is
--组建说明
--寄存器
component reg is
	port
	(
		clr: 		in	std_logic;
		D:		 	in	std_logic_vector(15 downto 0);
		clock:		in	std_logic;
		write:		in	std_logic;
	    sel:		in	std_logic;
		Q:		 	out	std_logic_vector(15 downto 0)
	);	
end component;
--加法器
component adder16 is
	PORT (
		a    : IN  std_logic_vector(15 DOWNTO 0);
		b    : IN  std_logic_vector(15 DOWNTO 0);
		cin  : IN  std_logic;
		sum  : OUT std_logic_vector(15 DOWNTO 0);
		cout  : OUT std_logic);
end component;
--减法器
component sub16 is
	PORT (
		A    : IN  std_logic_vector(15 DOWNTO 0);
		B    : IN  std_logic_vector(15 DOWNTO 0);
		cin  : IN  std_logic;
		S_sum  : OUT std_logic_vector(15 DOWNTO 0);
		cout  : OUT std_logic);
END component;

signal z_tmp,C_tmp1,C_tmp2:std_logic;
signal A,B,add_temp,sub_temp :std_logic_vector(15 downto 0);
signal result_t:  std_logic_vector(16 downto 0);

begin
--A寄存器映射
A_reg: reg port map
	(clr		=> reset,	
	 D			=> Dinput,	
	 clock		=> clk,		
	 write		=> write,		
	 sel		=> (not sel),		
	 Q			=> A
	);	
--B寄存器映射	
B_reg: reg port map
	(clr		=> reset,		
	 D			=> Dinput,	
	 clock		=> clk,		
	 write		=> write,		
	 sel		=> sel,		
	 Q			=> B
	);
--加法器和减法器映射
l2:sub16
   port map(A,B,'0',sub_temp,C_tmp2);
l1:adder16
   port map(A,B,'0',add_temp,C_tmp1);
--处理过程
alu_proc:process(OP,A,B)
begin
	case OP is
		when "0000" =>
--			result_t <= ('0' & A) + ('0' & B);
			result_t(15 downto 0)<=add_temp;
			result_t(16)<=C_tmp1;
	    when "0001" =>
--			result_t <= ('0' & A) - ('0' & B);
			result_t(15 downto 0)<=sub_temp;
			result_t(16)<=C_tmp2;
		when "0010" =>
			result_t <= ('0' & A) and ('0' & B);
		when "0011" =>
			result_t <= ('0' & A) xor ('0' & B);
		when "0100" =>
			result_t <= ('0' & A) or ('0' & B);
		when "0101" =>
			result_t <=  ('0' & B);
		when "0110" =>
			result_t <= ('0' & A) -  '1';
 		when "0111" =>
			result_t <= ('0' & A) +  '1';
		when "1000" =>
			result_t(15 downto 1) <=B(14 downto 0);
			result_t(0)<='0';
		when "1001" =>
			result_t(13 downto 0) <=B(14 downto 1);
			result_t(14)<='0';
			result_t(15)<=B(0);		
		when "1010" =>
			result_t <= ('0' & A) + ('0' & B)+cin;
		when "1011" =>
			result_t <= ('0' & A) - ('0' & B)-cin;
		when "1100" =>
			result_t <= not ('0' & B);
		when "1101" =>
			result_t(15 downto 0) <= A(7 downto 0) * B(7 downto 0);
			result_t(16)<='0';
	--	when "1110" =>
--			result_t(15 downto 0)<= A / B;
		when others =>
			result_t <="00000000000000000";
	end case;
result <= result_t(15 downto 0);
end process;

z_tmp <= (not result_t(15)) and (not result_t(14)) and
		(not result_t(13)) and (not result_t(12)) and
		(not result_t(11)) and (not result_t(10)) and
		(not result_t(9)) and (not result_t(8)) and
		(not result_t(7)) and (not result_t(6)) and
		(not result_t(5)) and (not result_t(4)) and
		(not result_t(3)) and (not result_t(2)) and
		(not result_t(1)) and (not result_t(0));


c_proc: Process(reset,clk,result_t,OP)
begin
    if reset = '0' then
		C <= '0';
--	elsif clk'event and clk = '1' then
--	    if OP(2) = '0' then
	else		C <= result_t(16);
--		end if;
	end if;
end process;

z_proc: process(reset,clk,z_tmp,OP)
begin
   if reset = '0' then
		Z <= '0';
--	elsif clk'event and clk = '1' then
--	    if OP /= "111" then
else			Z <= z_tmp;
--        end if;
	end if;
end process;

end behav;