📄 yima.vhd
字号:
library ieee;
use ieee.std_logic_1164.all;
entity yima is
port(a,b,c,d:in std_logic;
y: inout std_logic_vector(14 downto 0));
end yima;
architecture one of yima is
signal indata:std_logic_vector (3 downto 0);
begin
indata<=d&c&b&a;
process(indata)
begin
case indata is
when "0000"=>y<="000000010000000";
when "0001"=>y<="000000100000000";
when "0010"=>y<="000001000000000";
when "0011"=>y<="000010000000000";
when "0100"=>y<="000100000000000";
when "0101"=>y<="001000000000000";
when "0110"=>y<="010000000000000";
when "0111"=>y<="100000000000000";
when "1001"=>y<="000000000000001";
when "1010"=>y<="000000000000010";
when "1011"=>y<="000000000000100";
when "1100"=>y<="000000000001000";
when "1101"=>y<="000000000010000";
when "1110"=>y<="000000000100000";
when "1111"=>y<="000000001000000";
when others=>y<="000000000000000";
end case;
end process;
end one;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -