📄 baheyouxiji.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity baheyouxiji is
port(bego,clk1,cp,left,right,clearhexin,clearxianshi:in std_logic;
q:inout std_logic_vector(14 downto 0);
y:out std_logic_vector(6 downto 0);
jiedi,zz,yy:out std_logic);
end baheyouxiji;
architecture one of baheyouxiji is
component bahe
port(bego,left,right,cp,clear:in std_logic;--CP 接q18脚
q:inout std_logic_vector (14 downto 0));
end component;
component xianshi
port(cle,clk1,clk9,clk10,clear,set:in std_logic;
y:out std_logic_vector(6 downto 0);
jiedi,q0,q1:out std_logic);
end component;
signal cl,zq,yq,lll,rrr:std_logic;
begin
cl<='0';
lll<=not left;
rrr<=not right;
u1:bahe port map(bego,lll,rrr,cp,clearhexin,q);
g1:xianshi port map(cl,clk1,q(14),q(0),clearxianshi,bego,y,jiedi,zq,yq);
zz<=zq;
yy<=yq;
end one;
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