📄 bahe.vhd
字号:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity bahe is
port(bego,left,right,cp,clear:in std_logic;--CP 接q18脚
q:inout std_logic_vector (14 downto 0));
end bahe;
architecture one of bahe is
component hexin
port(bego,over,left,right,cp,clear:in std_logic;
q:inout std_logic_vector (14 downto 0));
end component;
component control
port(zuoduan,youduan:in std_logic;
over:out std_logic);
end component;
component jicunqi
port(d,clk,en:in std_logic;
y:out std_logic);
end component;
signal l,r,ov:std_logic;
begin
g1:jicunqi port map(left,cp,bego,l);
g2:jicunqi port map(right,cp,bego,r);
p1:hexin port map(bego,ov,l,r,cp,clear,q);
n1:control port map(q(14),q(0),ov);
end one;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -