📄 dport16.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity dport16 is
port(
cin1 : in std_logic;
cin2 : in std_logic;
cout : in std_logic;
din1 : in std_logic_vector(15 downto 0);
din2 : in std_logic_vector(15 downto 0);
dout : out std_logic_vector(15 downto 0);
dio : inout std_logic_vector(15 downto 0)
);
end dport16;
architecture a of dport16 is
begin
process(cin1,cin2,cout,din1,din2,dio)
begin
if cin1='1' then
dio <= din1;
dout <= (others=>'Z');
elsif cin2='1' then
dio <= din2;
dout <= (others=>'Z');
--else
-- dio <=(others=>'Z');
--end if;
elsif cout='1' then
dio <=(others=>'Z');
dout <= dio;
else
dio <=(others=>'Z');
dout <= (others=>'Z');
end if;
end process;
end a;
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