代码搜索:std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/459978/7259818
vhd subcont.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity subcont is
PORT( clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
cont : OUT STD_LOGIC_VECTOR(7
www.eeworm.com/read/459978/7259828
vhd addcont.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity addcont is
PORT( clk : IN STD_LOGIC;
rst : IN STD_LOGIC;
cont : OUT STD_LOGIC_VECTOR(7
www.eeworm.com/read/459949/7261510
vhd reg32b.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG32B IS
PORT (LOAD:IN STD_LOGIC;
DIN:IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUT:OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
END REG32
www.eeworm.com/read/459533/7274099
vhd dcnt10.vhd
--DCNT10.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DCNT10 IS
PORT(CLK:IN STD_LOGIC;
LOAD:IN STD_LOGIC;
ENA:IN STD_LOGI
www.eeworm.com/read/459533/7274114
vhd dcnt6.vhd
--DCNT6.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DCNT6 IS
PORT(CLK:IN STD_LOGIC;
LOAD:IN STD_LOGIC;
ENA:IN STD_LOGIC;
www.eeworm.com/read/459533/7274117
vhd cnt10.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT10 IS
PORT(
CLK:IN STD_LOGIC;
CLR:IN STD_LOGIC;
ENA: IN STD_LOGIC;
CQ:OUT STD_LOGIC_VECTOR(3 DOW
www.eeworm.com/read/459533/7274249
vhd cnt3.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT3 IS
PORT(
CLK:IN STD_LOGIC;
CQ:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
CARRY_OUT:OUT STD_LOGIC );
END CN
www.eeworm.com/read/459533/7274251
vhd cnt6.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT6 IS
PORT(
CLK:IN STD_LOGIC;
CLR:IN STD_LOGIC;
ENA: IN STD_LOGIC;
CQ:OUT STD_LOGIC_VECTOR(3 DOWN
www.eeworm.com/read/459166/7279284
vhd alu.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity alu is
port
( br_in:in std_logic_vector(15 downto 0);
cs:in std_logic_vector(31 downto 0);
clk:in std_
www.eeworm.com/read/459166/7279296
vhd pc.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity pc is
port
( mbr_in:in std_logic_vector(7 downto 0);--mbr[15..8]
cs:in std_logic_vector(31 downto 0);