reg32b.vhd

来自「实现6位频率计」· VHDL 代码 · 共 16 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY REG32B IS
   PORT (LOAD:IN STD_LOGIC;
         DIN:IN STD_LOGIC_VECTOR(31 DOWNTO 0);
         DOUT:OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
END REG32B;
ARCHITECTURE behav OF REG32B IS
BEGIN
  PROCESS(LOAD,DIN)
   BEGIN
   IF LOAD'EVENT AND LOAD='1' THEN DOUT<=DIN;
   END IF;
  END PROCESS;
END behav;