📄 dcnt6.vhd
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--DCNT6.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY DCNT6 IS
PORT(CLK:IN STD_LOGIC;
LOAD:IN STD_LOGIC;
ENA:IN STD_LOGIC;
DATAIN:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
CQ:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
CARRY_OUT:OUT STD_LOGIC);
END ENTITY DCNT6;
ARCHITECTURE ART OF DCNT6 IS
SIGNAL CQI:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(CLK,LOAD,ENA)IS
BEGIN
IF LOAD='1' THEN
CQI<=DATAIN;
ELSIF CLK'EVENT AND CLK='1' THEN
IF ENA='1' THEN
IF CQI="0000"THEN CQI<="0101";
ELSE CQI<=CQI-'1';END IF;
END IF;
END IF;
END PROCESS;
PROCESS(CLK,CQI)IS
BEGIN
IF CLK'EVENT AND CLK='1' THEN
IF CQI="0000"THEN CARRY_OUT<='1';
ELSE CARRY_OUT<='0';END IF;
END IF;
END PROCESS;
CQ<=CQI;
END ARCHITECTURE ART;
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