pc.vhd

用VHDL语言设计简单的CPU

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity pc is
	port
	(	mbr_in:in std_logic_vector(7 downto 0);--mbr[15..8]
		cs:in std_logic_vector(31 downto 0);
		clk:in std_logic;
		pc_out:out std_logic_vector(7 downto 0)
	);
end pc;

architecture behave of pc is
begin
	process(clk)
		variable temp:std_logic_vector(7 downto 0);
		begin
			if clk'event and clk='1'then
				if cs(20)='1'then 
					temp:="00000000";--reset
				elsif cs(18)='1'then
					temp:=mbr_in;
				elsif cs(19)='1'then
					temp:=temp+1;--increment
				end if;
			pc_out<=temp;
			end if;
	end process;
end behave;