alu.vhd

用VHDL语言设计简单的CPU

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity alu is
	port
	(	br_in:in std_logic_vector(15 downto 0);
		cs:in std_logic_vector(31 downto 0);
		clk:in std_logic;
		accis0:out std_logic;
		acc:out std_logic_vector(15 downto 0)
	);
end alu;

architecture behave of alu is
signal temp:std_logic_vector(15 downto 0);
begin
accis0<='1'when temp="0000000000000000"else'0';
	process(clk)
		begin
			if clk'event and clk='1'then
				if cs(24)='1'then
					temp<="0000000000000000";--reset
				elsif cs(22)='1'then
					temp<=temp+br_in;--add
				elsif cs(23)='1'then
					temp<=temp-br_in;--sub
				elsif cs(25)='1'then
					temp<='0'&br_in(15 downto 1);--shiftr
				elsif cs(7)='1'then
					temp<=br_in(14 downto 0)&'0';--shiftl
				elsif cs(1)='1'then
					temp<=temp and br_in;--and
				elsif cs(2)='1'then
					temp<=temp or br_in;--or
				elsif cs(3)='1'then
					temp<=not temp;--not
				end if;
				acc<=temp;
			end if;
	end process;
end behave;