代码搜索：std
找到约 10,000 项符合「std」的源代码
代码结果 10,000
www.eeworm.com/read/465285/7052762
vhd fred.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.ALL;
ENTITY fred IS
PORT
(
clk : IN STD_LOGIC;
num : in STD_LOGIC_VECTOR(3 DOWNTO 0
www.eeworm.com/read/464933/7063102
vhd segment7.vhd
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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
---------------------------------------
ENTITY segment7 IS
PORT (CLK: IN STD_
www.eeworm.com/read/464953/7063685
vhd insertb.vhd
--输出端用“11”表示符号“V”，“01”表示“1”码， “00”表示“0”码，“10”表示符号“B”。
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity insertb is
port( clk : in std_logic;
co
www.eeworm.com/read/464588/7065918
vhd mcutofpga.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity McuToFpga is
generic(QWidth : Integer := 24); --移位寄存器的宽度
port(
CLK: in std_logic; --同步时钟,上升研写入数据
DA
www.eeworm.com/read/464588/7065920
vhd dds.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dds is
port(
frep: in std_logic_vector(14 downto 0);
phase: in std_logic_vector(8 downto 0);
www.eeworm.com/read/119976/7086798
vhd myfunction.vhd
Library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
package MyFunc IS
Function max(L, R: INTEGER) return INTEGER ;
Function "+"(L:STD_LOGIC_VECTOR;R:STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
END Pac
www.eeworm.com/read/369273/7099392
vhd shuzi.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY SHUZI IS
PORT(DIAO,GONG,RST,CLK1,CLK2:IN STD_LOGIC;
C0:OUT STD_LOGIC;
Y:OUT STD_LOGIC_VECTOR
www.eeworm.com/read/369273/7099582
bak sm.vhd.bak
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SM IS
PORT(CLK2:IN STD_LOGIC;
MIAO,FEN,SHI:IN STD_LOGIC_VECTOR (7 DOWNTO 0);
Y: OUT STD_LOGIC_VECTOR
www.eeworm.com/read/369273/7099584
vhd sm.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SM IS
PORT(CLK2:IN STD_LOGIC;
MIAO,FEN,SHI:IN STD_LOGIC_VECTOR (7 DOWNTO 0);
Y: OUT STD_LOGIC_VECTOR
www.eeworm.com/read/369273/7099749
vhd sm.vhd
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SM IS
PORT(CLK2:IN STD_LOGIC;
MIAO,FEN,DIAN:IN STD_LOGIC_VECTOR (7 DOWNTO 0);
Y: OUT STD_LOGIC_VECTOR