shuzi.vhd

可预置数字钟

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY SHUZI IS
 PORT(DIAO,GONG,RST,CLK1,CLK2:IN STD_LOGIC;
                           C0:OUT STD_LOGIC;
                         Y:OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
                CQ:OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END ENTITY SHUZI;
ARCHITECTURE fd1 OF SHUZI IS
COMPONENT ZT
 PORT(GONG,RST : IN STD_LOGIC;
     ZHUANG:OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END COMPONENT ;
COMPONENT JW
 PORT(DIAO,CLK1,CO1,CO2:IN STD_LOGIC;
                ZHUANG: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
           JW1,JW2,JW3:OUT STD_LOGIC );
END COMPONENT ;
COMPONENT SHIZHI
PORT(RST,DIAO: IN STD_LOGIC;
     ZHUANG: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
     SZ: OUT STD_LOGIC_VECTOR(7 DOWNTO 0 ));
END COMPONENT ;
COMPONENT F_M
PORT (RST,JW : IN STD_LOGIC;
        FM : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
        CO : OUT STD_LOGIC );
END COMPONENT ;
COMPONENT SHI
PORT ( JW,RST: IN STD_LOGIC;
             SZ: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
             XS: OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END COMPONENT ;
COMPONENT SM
PORT(CLK2:IN STD_LOGIC;
     MIAO,FEN,DIAN:IN STD_LOGIC_VECTOR (7 DOWNTO 0);
     Y: OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
     CQ: OUT STD_LOGIC_VECTOR (3 DOWNTO 0));
END COMPONENT ;
SIGNAL a,b,c,d,e:STD_LOGIC;
SIGNAL j:STD_LOGIC_VECTOR (2 DOWNTO 0);
SIGNAL f,g,h,i:STD_LOGIC_VECTOR (7 DOWNTO 0);
 BEGIN
 u1:ZT PORT MAP(GONG=>GONG,RST=>RST,ZHUANG=>j);
 u2:JW PORT MAP(CLK1=>CLK1,DIAO=>DIAO,ZHUANG=>j,CO1=>d,CO2=>e,JW1=>a,JW2=>b,JW3=>c);
 u3:SHIZHI PORT MAP(RST=>RST,DIAO=>DIAO,ZHUANG=>j,SZ=>f);
 u4:F_M PORT MAP(JW=>a,RST=>RST,CO=>d,FM=>h);
 u5:F_M PORT MAP(JW=>b,RST=>RST,CO=>e,FM=>i);
 u6:SHI PORT MAP(JW=>c,RST=>RST,SZ=>f,XS=>g);
 u7:SM PORT MAP(MIAO=>h,FEN=>i,DIAN=>g,CLK2=>CLK2,CQ=>CQ,Y=>Y);
C0<='1'WHEN j="000" ELSE '0';

END ARCHITECTURE fd1;