fred.vhd

用FPGA仿真实现数控分频器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.ALL;
ENTITY fred IS
	PORT
	(
		clk		: IN	STD_LOGIC;
		num		: in	STD_LOGIC_VECTOR(3 DOWNTO 0);
		fout	: out	STD_LOGIC
	);
END fred ;

ARCHITECTURE a OF fred  IS
	SIGNAL dats : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
processl:
	PROCESS (clk)
	BEGIN	

IF clk'event and clk='1' THEN
	if dats=num then 
	fout<= '1';
	dats<="0000";
	else 
	dats<=dats+1;
	fout<= '0';
	end if;
END IF;
	END PROCESS processl;
END a;