sm.vhd

来自「可预置数字钟」· VHDL 代码 · 共 30 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SM IS
PORT(CLK2:IN STD_LOGIC;
     MIAO,FEN,SHI:IN STD_LOGIC_VECTOR (7 DOWNTO 0);
     Y: OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
     CQ: OUT STD_LOGIC_VECTOR (3 DOWNTO 0));
END SM;
ARCHITECTURE behav OF SM IS
SIGNAL BT :     STD_LOGIC_VECTOR (2 DOWNTO 0);
BEGIN
PROCESS(CLK2)
  BEGIN
    IF CLK2'EVENT AND CLK2='1' THEN 
     IF BT<"101" THEN    BT<=BT+1;
      ELSE BT<="000";
     END IF;
     END IF;
    CASE BT IS
     WHEN  "000"=> Y<="000" ;CQ<=MIAO(3 DOWNTO 0);
     WHEN  "001"=> Y<="001" ;CQ<=MIAO(7 DOWNTO 4);
     WHEN  "010"=> Y<="010" ;CQ<=FEN(3 DOWNTO 0);
     WHEN  "011"=> Y<="011" ;CQ<=FEN(7 DOWNTO 4);
     WHEN  "100"=> Y<="100" ;CQ<=SHI(3 DOWNTO 0);
     WHEN  "101"=> Y<="101" ;CQ<=SHI(7 DOWNTO 4);
     WHEN  OTHERS =>  NULL;
    END CASE;
  END PROCESS;
END behav;