segment7.vhd

来自「上海交通大学VHDL课程的所有作业代码」· VHDL 代码 · 共 43 行

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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
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ENTITY segment7 IS
	PORT (CLK: IN STD_LOGIC;
			ledr0,ledr1,ledr2,ledr3: BUFFER STD_LOGIC;
			hex0: BUFFER std_logic_vector(0 to 6);
			hex1: BUFFER std_logic_vector(0 to 6);
			SWITCH: IN STD_LOGIC_VECTOR(0 TO 3));
	END segment7;
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ARCHITECTURE example OF segment7 IS
BEGIN
	PROCESS (CLK)
  BEGIN
	case SWITCH is
		when "0000" => hex1<="0000001"; hex0<="0000001";  --0
		when "0001" => hex1<="0000001"; hex0<="1001111";  --1
		when "0010" => hex1<="0000001"; hex0<="0010010";  --2
		when "0011" => hex1<="0000001"; hex0<="0000110";  --3
		when "0100" => hex1<="0000001"; hex0<="1001100";  --4
		when "0101" => hex1<="0000001"; hex0<="0100100";  --5
		when "0110" => hex1<="0000001"; hex0<="0100000";  --6
		when "0111" => hex1<="0000001"; hex0<="0001111";  --7
		when "1000" => hex1<="0000001"; hex0<="0000000";  --8
		when "1001" => hex1<="0000001"; hex0<="0001100";  --9
		when "1010" => hex1<="1001111"; hex0<="0000001";  --10
		when "1011" => hex1<="1001111"; hex0<="1001111";  --11
		when "1100" => hex1<="1001111"; hex0<="0010010";  --12
		when "1101" => hex1<="1001111"; hex0<="0000110";  --13
		when "1110" => hex1<="1001111"; hex0<="1001100";  --14
		when "1111" => hex1<="1001111"; hex0<="0100100";  --15
	end case;
	end process;	
	ledr3<= SWITCH(3);
	ledr2<= SWITCH(2);
	ledr1<= SWITCH(1);
	ledr0<= SWITCH(0);

end example;