maj1.vhd

来自「上海交通大学VHDL课程的所有作业代码」· VHDL 代码 · 共 19 行

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY maj1 IS
PORT (a, b, c :   	 IN BIT;
m :      	OUT BIT);
END maj1;
ARCHITECTURE using_table OF maj1 IS
BEGIN
PROCESS (a, b, c)
CONSTANT lookuptable : 	BIT_VECTOR(0 TO 7) := "00010111";
VARIABLE index : NATURAL;
BEGIN
Index := 0; --index must be cleared each time process executes
IF a = '1' THEN index := index + 1; END IF;
IF b = '1' THEN index := index + 2; END IF;
IF c = '1' THEN index := index + 4; END IF;
m <= lookuptable(index);
END PROCESS;
END using_table;